Power Consumption
Typical 5.0V Power Consumption
CY37032
60
50
Ultra37000 CPLD Family
High S peed
40
Low Power
30
20
10
CY37064
0
0
90
80
70
60
50
40
30
20
10
0
0
50
100
150
200
250
Frequency (M Hz)
The typical pattern is a 16-bit up counter, per logic block, with outputs disabled.
VCC = 5.0V, TA = Room Temperature
H igh S peed
Low Power
20
40
60
80
100
120
140
160
180
Frequency (M Hz)
The typical pattern is a 16-bit up counter, per logic block, with outputs disabled.
VCC = 5.0V, TA = Room Temperature
Document #: 38-03007 Rev. *C
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