5962-9952001QYA(2003) View Datasheet(PDF) - Cypress Semiconductor
Part Name
Description
Manufacturer
5962-9952001QYA Datasheet PDF : 62 Pages
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Ultra37000 CPLD Family
Switching Characteristics Over the Operating Range[12] (continued)
Parameter
Description
tWH
Clock or Latch Enable Input HIGH Time[8]
tIS
Input Register or Latch Set-up Time
tIH
tICO[13, 14, 15]
tICOL[13, 14, 15]
Input Register or Latch Hold Time
Input Register Clock or Latch Enable to Combinatorial Output
Input Register Clock or Latch Enable to Output Through Transparent Output Latch
Synchronous Clocking Parameters
tCO[14, 15]
tS[13]
Synchronous Clock (CLK0, CLK1, CLK2, or CLK3) or Latch Enable to Output
Set-Up Time from Input to Sync. Clk (CLK0, CLK1, CLK2, or CLK3) or Latch Enable
tH
tCO2[13, 14, 15]
Register or Latch Data Hold Time
Output Synchronous Clock (CLK0, CLK1, CLK2, or CLK3) or Latch Enable to Combinatorial Output
Delay (Through Logic Array)
tSCS[13]
tSL[13]
Output Synchronous Clock (CLK0, CLK1, CLK2, or CLK3) or Latch Enable to Output Synchronous
Clock (CLK0, CLK1, CLK2, or CLK3) or Latch Enable (Through Logic Array)
Set-Up Time from Input Through Transparent Latch to Output Register Synchronous Clock (CLK0
CLK1, CLK2, or CLK3) or Latch Enable
tHL
Hold Time for Input Through Transparent Latch from Output Register Synchronous Clock (CLK0,
CLK1, CLK2, or CLK3) or Latch Enable
Product Term Clocking Parameters
tCOPT[13, 14, 15]
Product Term Clock or Latch Enable (PTCLK) to Output
tSPT
Set-Up Time from Input to Product Term Clock or Latch Enable (PTCLK)
tHPT
tISPT[13]
Register or Latch Data Hold Time
Set-Up Time for Buried Register used as an Input Register from Input to Product Term Clock or
Latch Enable (PTCLK)
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tIHPT
tCO2PT[13, 14, 15]
Buried Register Used as an Input Register or Latch Data Hold Time
Product Term Clock or Latch Enable (PTCLK) to Output Delay (Through Logic Array)
Pipelined Mode Parameters
tICS[13]
Input Register Synchronous Clock (CLK0, CLK1, CLK2, or CLK3) to Output Register Synchronous
Clock (CLK0, CLK1, CLK2, or CLK3)
Operating Frequency Parameters
fMAX1
Maximum Frequency with Internal Feedback (Lesser of 1/tSCS, 1/(tS + tH), or 1/tCO)[5]
fMAX2
fMAX3
Maximum Frequency Data
1/(tS + tH), or 1/tCO)[5]
Path
in
Output
Registered/Latched
Mode
(Lesser
of
1/(tWL
+
tWH),
Maximum Frequency with External Feedback (Lesser of 1/(tCO + tS) or 1/(tWL + tWH)[5]
fMAX4
Maximum Frequency
or 1/tSCS)[5]
in
Pipelined
Mode
(Lesser
of
1/(tCO
+
tIS),
1/tICS,
1/(tWL
+
tWH),
1/(tIS
+
tIH),
Reset/Preset Parameters
tRW
tRR[13]
tRO[13, 14, 15]
tPW
tPR[13]
tPO[13, 14, 15]
Asynchronous Reset Width[5]
Asynchronous Reset Recovery Time[5]
Asynchronous Reset to Output
Asynchronous Preset Width[5]
Asynchronous Preset Recovery Time[5]
Asynchronous Preset to Output
User Option Parameters
ns
ns
ns
MHz
MHz
MHz
MHz
ns
ns
ns
ns
ns
ns
tLP
Low Power Adder
ns
tSLEW
Slow Output Slew Rate Adder
ns
t3.3IO
3.3V I/O Mode Timing Adder[5]
ns
Document #: 38-03007 Rev. *C
Page 18 of 62
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