CS4334/5/8/9
LRCK
t slrd
t slrs
t sclkh
t sclkl
SCLK
t sdlrs
t sdh
SDATA
Figure 4. External Serial Mode Input Timing
LRCK
t sclkr
SDATA
t sdlrs t sdh
t sclkw
*INTERNAL SCLK
Figure 5. Internal Serial Mode Input Timing
* The SCLK pulses shown are internal to the CS4334/5/8/9.
LRCK
MCLK
1
N
N
2
*INTERNAL SCLK
SDATA
Figure 6. Internal Serial Clock Generation
* The SCLK pulses shown are internal to the CS4334/5/8/9.
N equals MCLK divided by SCLK
10
DS248F3