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COP684CS View Datasheet(PDF) - National ->Texas Instruments

Part NameCOP684CS National-Semiconductor
National ->Texas Instruments National-Semiconductor
Description8-Bit CMOS ROM Based Microcontrollers with 4k to 24k Memory, Comparators and USART
COP684CS Datasheet PDF : 53 Pages
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Interrupts (Continued)
Pending Flag
There is a pending flag bit associated with the non-maskable
interrupt, called STPND. This pending flag is not memory-
mapped and cannot be accessed directly by the software.
The pending flag is reset to zero when a device Reset oc-
curs. When the non-maskable interrupt occurs, the associ-
ated pending bit is set to 1. The interrupt service routine
should contain an RPND instruction to reset the pending flag
to zero. The RPND instruction always resets the STPND
Software Trap
The Software Trap is a special kind of non-maskable inter-
rupt which occurs when the INTR instruction (used to ac-
knowledge interrupts) is fetched from program memory and
placed in the instruction register. This can happen in a vari-
ety of ways, usually because of an error condition. Some ex-
amples of causes are listed below.
If the program counter incorrectly points to a memory loca-
tion beyond the available program memory space, the non-
existent or unused memory location returns zeroes which is
interpreted as the INTR instruction.
If the stack is popped beyond the allowed limit (address 06F
Hex), a 7FFF will be loaded into the PC, if this last location in
program memory is unprogrammed or unavailable, a Soft-
ware Trap will be triggered.
A Software Trap can be triggered by a temporary hardware
condition such as a brownout or power supply glitch.
The Software Trap has the highest priority of all interrupts.
When a Software Trap occurs, the STPND bit is set. The GIE
bit is not affected and the pending bit (not accessible by the
user) is used to inhibit other interrupts and to direct the pro-
gram to the ST service routine with the VIS instruction. Noth-
ing can interrupt a Software Trap service routine except for
another Software Trap. The STPND can be reset only by the
RPND instruction or a chip Reset.
The Software Trap indicates an unusual or unknown error
condition. Generally, returning to normal execution at the
point where the Software Trap occurred cannot be done re-
liably. Therefore, the Software Trap service routine should
reinitialize the stack pointer and perform a recovery proce-
dure that restarts the software at some known point, similar
to a device Reset, but not necessarily performing all the
same functions as a device Reset. The routine must also ex-
ecute the RPND instruction to reset the STPND flag. Other-
wise, all other interrupts will be locked out. To the extent pos-
sible, the interrupt routine should record or indicate the
context of the device so that the cause of the Software Trap
can be determined.
If the user wishes to return to normal execution from the
point at which the Software Trap was triggered, the user
must first execute RPND, followed by RETSK rather than
RETI or RET. This is because the return address stored on
the stack is the address of the INTR instruction that triggered
the interrupt. The program must skip that instruction in order
to proceed with the next one. Otherwise, an infinite loop of
Software Traps and returns will occur.
Programming a return to normal execution requires careful
consideration. If the Software Trap routine is interrupted by
another Software Trap, the RPND instruction in the service
routine for the second Software Trap will reset the STPND
flag; upon return to the first Software Trap routine, the
STPND flag will have the wrong state. This will allow
maskable interrupts to be acknowledged during the servicing
of the first Software Trap. To avoid problems such as this, the
user program should contain the Software Trap routine to
perform a recovery procedure rather than a return to normal
Under normal conditions, the STPND flag is reset by a
RPND instruction in the Software Trap service routine. If a
programming error or hardware condition (brownout, power
supply glitch, etc.) sets the STPND flag without providing a
way for it to be cleared, all other interrupts will be locked out.
To alleviate this condition, the user can use extra RPND in-
structions in the main program and in the WATCHDOG ser-
vice routine (if present). There is no harm in executing extra
RPND instructions in these parts of the program.
Port L provides the user with an additional eight fully select-
able, edge sensitive interrupts which are all vectored into the
same service subroutine.
The interrupt from Port L shares logic with the wake up cir-
cuitry. The register WKEN allows interrupts from Port L to be
individually enabled or disabled. The register WKEDG speci-
fies the trigger condition to be either a positive or a negative
edge. Finally, the register WKPND latches in the pending
trigger conditions.
The GIE (Global Interrupt Enable) bit enables the interrupt
A control flag, LPEN, functions as a global interrupt enable
for Port L interrupts. Setting the LPEN flag will enable inter-
rupts and vice versa. A separate global pending flag is not
needed since the register WKPND is adequate.
Since Port L is also used for waking the device out of the
HALT or IDLE modes, the user can elect to exit the HALT or
IDLE modes either with or without the interrupt enabled. If he
elects to disable the interrupt, then the device will restart ex-
ecution from the instruction immediately following the in-
struction that placed the microcontroller in the HALT or IDLE
modes. In the other case, the device will first execute the in-
terrupt service routine and then revert to normal operation.
(See HALT MODE for clock option wakeup information.)
The device uses the following types of interrupts, listed be-
low in order of priority:
1. The Software Trap non-maskable interrupt, triggered by
the INTR (00 opcode) instruction. The Software Trap is
acknowledged immediately. This interrupt service rou-
tine can be interrupted only by another Software Trap.
The Software Trap should end with two RPND instruc-
tions followed by a restart procedure.
2. Maskable interrupts, triggered by an on-chip peripheral
block or an external device connected to the device. Un-
der ordinary conditions, a maskable interrupt will not in-
terrupt any other interrupt routine in progress. A
maskable interrupt routine in progress can be inter-
rupted by the non-maskable interrupt request. A
maskable interrupt routine should end with an RETI in-
struction or, prior to restoring context, should return to
execute the VIS instruction. This is particularly useful
when exiting long interrupt service routiness if the time
between interrupts is short. In this case the RETI instruc-
tion would only be executed when the default VIS rou-
tine is reached.
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