Baud Clock Generation (Continued)
As an example, considering Asynchronous Mode and a CKI
clock of 4.608 MHz, the prescaler factor selected is:
4.608/1.8432 = 2.5
The 2.5 entry is available in Table 4. The 1.8432 MHz pres-
caler output is then used with proper Baud Rate Divisor
(Table 3) to obtain different baud rates. For a baud rate of
19200 e.g., the entry in Table 3 is 5.
N − 1 = 5 (N − 1 is the value from Table 3)
N = 6 (N is the Baud Rate Divisor)
Baud Rate = 1.8432 MHz/(16 x 6) = 19200
The divide by 16 is performed because in the asynchronous
mode, the input frequency to the USART is 16 times the
baud rate. The equation to calculate baud rates is given be-
The actual Baud Rate may be found from:
BR = Fc/(16 x N x P)
BR is the Baud Rate
Fc is the CKI frequency
N is the Baud Rate Divisor (Table 3).
P is the Prescaler Divide Factor selected by the value in the
Prescaler Select Register (Table 4)
Note: In the Synchronous Mode, the divisor 16 is replaced by two.
Crystal Frequency = 5 MHz
Desired baud rate = 9600
Using the above equation N x P can be calculated first.
N x P = (5 x 106)/(16 x 9600) = 32.552
Now 32.552 is divided by each Prescaler Factor (Table 4) to
obtain a value closest to an integer. This factor happens to
be 6.5 (P = 6.5).
N = 32.552/6.5 = 5.008 (N = 5)
The programmed value (from Table 3) should be 4 (N − 1).
Using the above values calculated for N and P:
BR = (5 x 106)/(16 x 5 x 6.5) = 9615.384
% error = (9615.385 − 9600)/9600 x 100 = 0.16%
Effect of HALT/IDLE
The USART logic is reinitialized when either the HALT or
IDLE modes are entered. This reinitialization sets the TBMT
flag and resets all read only bits in the USART control and
status registers. Read/Write bits remain unchanged. The
Transmit Buffer (TBUF) is not affected, but the Transmit Shift
register (TSFT) bits are set to one. The receiver registers
RBUF and RSFT are not affected.
The device will exit from the HALT/IDLE modes when the
Start bit of a character is detected at the RDX (L3) pin. This
feature is obtained by using the Multi-Input Wakeup scheme
provided on the device.
Before entering the HALT or IDLE modes the user program
must select the Wakeup source to be on the RDX pin. This
selection is done by setting bit 3 of WKEN (Wakeup Enable)
register. The Wakeup trigger condition is then selected to be
high to low transition. This is done via the WKEDG register
(Bit 3 is one.)
If the device is halted and crystal oscillator is used, the
Wakeup signal will not start the chip running immediately be-
cause of the finite start up time requirement of the crystal os-
cillator. The idle timer (T0) generates a fixed (256 tc) delay to
ensure that the oscillator has indeed stabilized before allow-
ing the device to execute code. The user has to consider this
delay when data transfer is expected immediately after exit-
ing the HALT mode.
Bits CHARL0 and CHARL1 in the ENU register provide a
loopback feature for diagnostic testing of the USART. When
these bits are set to one, the following occur: The receiver in-
put pin (RDX) is internally connected to the transmitter out-
put pin (TDX); the output of the Transmitter Shift Register is
“looped back” into the Receive Shift Register input. In this
mode, data that is transmitted is immediately received. This
feature allows the processor to verify the transmit and re-
ceive data paths of the USART.
Note that the framing format for this mode is the nine bit for-
mat; one Start bit, nine data bits, and 7/8, one or two Stop
bits. Parity is not generated or verified in this mode.
The USART Receiver section supports an alternate mode of
operation, referred to as ATTENTION Mode. This mode of
operation is selected by the ATTN bit in the ENUR register.
The data format for transmission must also be selected as
having nine Data bits and either 7/8, one or two Stop bits.
The ATTENTION mode of operation is intended for use in
networking the device with other processors. Typically in
such environments the messages consists of device ad-
dresses, indicating which of several destinations should re-
ceive them, and the actual data. This Mode supports a
scheme in which addresses are flagged by having the ninth
bit of the data field set to a 1. If the ninth bit is reset to a zero
the byte is a Data byte.
While in ATTENTION mode, the USART monitors the com-
munication flow, but ignores all characters until an address
character is received. Upon receiving an address character,
the USART signals that the character is ready by setting the
RBFL flag, which in turn interrupts the processor if USART
Receiver interrupts are enabled. The ATTN bit is also cleared
automatically at this point, so that data characters as well as
address characters are recognized. Software examines the
contents of the RBUF and responds by deciding either to ac-
cept the subsequent data stream (by leaving the ATTN bit re-
set) or to wait until the next address character is seen (by
setting the ATTN bit again).
Operation of the USART Transmitter is not affected by selec-
tion of this Mode. The value of the ninth bit to be transmitted
is programmed by setting XBIT9 appropriately. The value of
the ninth bit received is obtained by reading RBIT9. Since
this bit is located in ENUR register where the error flags re-
side, a bit operation on it will reset the error flags.
The device contains two differential comparators, each with
a pair of inputs (positive and negative) and an output. Ports
I1–I3 and I4–I6 are used for the comparators. The following
is the Port I assignment:
I6 Comparator2 output
I5 Comparator2 positive input
I4 Comparator2 negative input
I3 Comparator1 output