ADSP-218xN Series
Mini-BGA Package Pinout
The Mini-BGA package pinout is shown in the illustration
below and in Table 28. Pin names in bold text in the table
replace the plain text named functions when Mode C = 1.
A + sign separates two functions when either function can
be active for either major I/O mode. Signals enclosed in
brackets [ ] are state bits latched from the value of the pin
at the deassertion of RESET. The multiplexed pins
DT1/FO, TFS1/IRQ1, RFS1/IRQ0, and DR1/FI, are mode
selectable by setting Bit 10 (SPORT1 configure) of the
System Control Register. If Bit 10 = 1, these pins have serial
port functionality. If Bit 10 = 0, these pins are the external
interrupt and flag pins. This bit is set to 1 by default upon
reset.
144-BALL MINI-BGA PACKAGE PINOUT (BOTTOM VIEW)
12
11
10
9
8
7
6
5
4
3
2
1
GND
GND
D22
NC
NC
NC
GND
NC
A0
GND
A1/IAD0 A2/IAD1
A
D16
D17
D18
D20
D23
VDDEXT
GND
NC
NC
GND
A3/IAD2 A4/IAD3
B
D14
GND
D10
D9
NC
D15
D19
D21
VDDEXT
PWD
A7/IAD6
A5/IAD4
RD
A6/IAD5
PWDACK C
NC
D12
GND
VDDEXT
D13
GND
NC
PF2
PF1
[MODE C] [MODE B]
A9/IAD8
BGH
NC
WR
NC
D
GND
PF3
[MODE D]
FL2
PF0
[MODE A]
FL0
A8/IAD7
VDDEXT
VDDEXT
E
NC
D8
D11
D7/IWR
NC
NC
FL1
A11/IAD10 A12/IAD11
NC
A13/IAD12 F
D4/IS
NC
NC
D5/IAL
D6/IRD
NC
NC
NC
A10/IAD9
GND
NC
XTAL
G
GND
NC
GND
D3/IACK D2/IAD15
TFS0
DT0
VD D I N T
GND
GND
GND
CLKIN
H
VDDINT
VD D I N T
D1/IAD14
BG
RFS1/IRQ0 D0/IAD13
SC L K0
VDDEXT
VDDEXT
EBG
BR
EBR
ERESET
SC L K1
TFS1/IRQ1
RFS0
DMS
BMS
NC
VD D I NT
CLKOUT
J
NC
NC
NC
K
EINT
ELOUT
ELIN
RESET
GND
DR0
PMS
GND
IOMS IRQL1 + PF6
NC IRQ E + PF 4 L
ECLK
EE
EMS
NC
GND
DR1/FI
DT1/FO
GND
CMS
NC IRQ 2 + PF 7 I RQ L 0 + PF 5 M
REV. 0
–41–