ADSP-2187NKCA-320 View Datasheet(PDF) - Analog Devices
Part Name
Description
Manufacturer
ADSP-2187NKCA-320 Datasheet PDF : 45 Pages
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ADSP-218xN Series
GND
EBG
EBR
KEY (NO PIN)
ELOUT
EE
RESET
1
2
3
4
5
6
7
8
؋
9
10
11
12
13
14
TOP VIEW
BG
BR
EINT
ELIN
ECLK
EMS
ERESET
Figure 15. Target Board Connector for EZ-ICE
Pin spacing should be 0.1 ؋ 0.1 inches. The pin strip header
must have at least 0.15 inch clearance on all sides to accept
the EZ-ICE probe plug.
Pin strip headers are available from vendors such as 3M,
McKenzie, and Samtec.
Target Memory Interface
For the target system to be compatible with the EZ-ICE
emulator, it must comply with the memory interface guide-
lines listed below.
PM, DM, BM, IOM, and CM
Design the Program Memory (PM), Data Memory (DM),
Byte Memory (BM), I/O Memory (IOM), and Composite
Memory (CM) external interfaces to comply with worst-
case device timing requirements and switching characteris-
tics as specified in this data sheet. The performance of the
EZ-ICE may approach published worst-case specification
for some memory access timing requirements and switching
characteristics.
Note: If the target does not meet the worst-case chip spec-
ification for memory access parameters, the circuitry may
not be able to be emulated at the desired CLKIN frequency.
Depending on the severity of the specification violation, the
system may be difficult to manufacture, as DSP compo-
nents statistically vary in switching characteristic and timing
requirements, within published limits.
Restriction: All memory strobe signals on the ADSP-
218xN (RD, WR, PMS, DMS, BMS, CMS, and IOMS)
used in the target system must have 10 k⍀ pull-up resistors
connected when the EZ-ICE is being used. The pull-up
resistors are necessary because there are no internal pull-
ups to guarantee their state during prolonged three-state
conditions resulting from typical EZ-ICE debugging ses-
sions. These resistors may be removed when the EZ-ICE is
not being used.
Target System Interface Signals
When the EZ-ICE board is installed, the performance on
some system signals changes. Design the system to be com-
patible with the following system interface signal changes
introduced by the EZ-ICE board:
• EZ-ICE emulation introduces an 8 ns propagation
delay between the target circuitry and the DSP on the
RESET signal.
• EZ-ICE emulation introduces an 8 ns propagation
delay between the target circuitry and the DSP on the BR
signal.
• EZ-ICE emulation ignores RESET and BR, when
single-stepping.
• EZ-ICE emulation ignores RESET and BR when in
Emulator Space (DSP halted).
• EZ-ICE emulation ignores the state of target BR in certain
modes. As a result, the target system may take control of
the DSP’s external memory bus only if bus grant (BG) is
asserted by the EZ-ICE board’s DSP.
–20–
REV. 0
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