ADSP-2187NBCA-320 View Datasheet(PDF) - Analog Devices

Part Name

Description

Manufacturer

ADSP-2187NBCA-320

DSP Microcomputer

Analog Devices 

ADSP-218xN Series

and IDPMOVLAY bits in the IDMA overlay register as

indicated in Table 12. Refer to the ADSP-218x DSP Hard-

ware Reference for additional details.

Note: In full memory mode all locations of 4M-byte

memory space are directly addressable. In host memory

mode, only address pin A0 is available, requiring additional

external logic to provide address information for the byte.

IDMA OVERLAY

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DM (0x3FE7)

RESERVED SET TO 0

RESERVED SET TO 0

IDDMOVLAY IDPMOVLAY

(SEE TABLE 12)

SHORT READ ONLY

0 = DISABLE

1 = ENABLE

IDMA CONTROL (U = UNDEFINED AT RESET)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 U U U U U U U U U U U U U U U DM (0x3FE0)

IDMAA ADDRESS

RESERVED SET TO 0

IDMAD DESTINATION MEMORY

TYPE

0 = PM

1 = DM

NOTE: RESERVED BITS ARE SHOWN ON A GRAY FIELD. THESE

BITS SHOULD ALWAYS BE WRITTEN WITH ZEROS.

Figure 13. IDMA OVLAY/Control Registers

Bootstrap Loading (Booting)

ADSP-218xN series members have two mechanisms to

allow automatic loading of the internal program memory

after reset. The method for booting is controlled by the

Mode A, B, and C configuration bits.

When the mode pins specify BDMA booting, the ADSP-

218xN initiates a BDMA boot sequence when reset is

released.

The BDMA interface is set up during reset to the following

defaults when BDMA booting is specified: the BDIR,

BMPAGE, BIAD, and BEAD registers are set to 0, the

BTYPE register is set to 0 to specify program memory 24-

bit words, and the BWCOUNT register is set to 32. This

causes 32 words of on-chip program memory to be loaded

from byte memory. These 32 words are used to set up the

BDMA to load in the remaining program code. The BCR

bit is also set to 1, which causes program execution to be

held off until all 32 words are loaded into on-chip program

memory. Execution then begins at address 0.

The ADSP-2100 Family development software (Revision

5.02 and later) fully supports the BDMA booting feature

and can generate byte memory space-compatible boot code.

The IDLE instruction can also be used to allow the proces-

sor to hold off execution while booting continues through

the BDMA interface. For BDMA accesses while in Host

Mode, the addresses to boot memory must be constructed

externally to the ADSP-218xN. The only memory address

bit provided by the processor is A0.

IDMA Port Booting

ADSP-218xN series members can also boot programs

through its Internal DMA port. If Mode C = 1, Mode B =

0, and Mode A = 1, the ADSP-218xN boots from the IDMA

port. IDMA feature can load as much on-chip memory as

desired. Program execution is held off until the host writes

to on-chip program memory location 0.

BUS REQUEST AND BUS GRANT

ADSP-218xN series members can relinquish control of the

data and address buses to an external device. When the

external device requires access to memory, it asserts the Bus

Request (BR) signal. If the ADSP-218xN is not performing

an external memory access, it responds to the active BR

input in the following processor cycle by:

• Three-stating the data and address buses and the PMS,

DMS, BMS, CMS, IOMS, RD, WR output drivers,

• Asserting the bus grant (BG) signal, and

• Halting program execution.

If Go Mode is enabled, the ADSP-218xN will not halt

program execution until it encounters an instruction that

requires an external memory access.

If an ADSP-218xN series member is performing an external

memory access when the external device asserts the BR

signal, it will not three-state the memory interfaces nor

assert the BG signal until the processor cycle after the access

completes. The instruction does not need to be completed

when the bus is granted. If a single instruction requires two

external memory accesses, the bus will be granted between

the two accesses.

When the BR signal is released, the processor releases the

BG signal, re-enables the output drivers, and continues

program execution from the point at which it stopped.

The bus request feature operates at all times, including

when the processor is booting and when RESET is active.

The BGH pin is asserted when an ADSP-218xN series

member requires the external bus for a memory or BDMA

access, but is stopped. The other device can release the bus

by deasserting bus request. Once the bus is released, the

ADSP-218xN deasserts BG and BGH and executes the

external memory access.

FLAG I/O PINS

ADSP-218xN series members have eight general-purpose

programmable input/output flag pins. They are controlled

by two memory-mapped registers. The PFTYPE register

determines the direction, 1 = output and 0 = input. The

PFDATA register is used to read and write the values on the

pins. Data being read from a pin configured as an input is

synchronized to the ADSP-218xN’s clock. Bits that are pro-

grammed as outputs will read the value being output. The

PF pins default to input during reset.

–18–

REV. 0

Share Link: