ADSP-2187NKST-320 View Datasheet(PDF) - Analog Devices

Part Name

Description

Manufacturer

ADSP-2187NKST-320

DSP Microcomputer

Analog Devices 

ADSP-218xN Series

DSP cycle. DSP accesses to external memory have priority

over BDMA byte memory accesses.

The BDMA Context Reset bit (BCR) controls whether the

processor is held off while the BDMA accesses are occur-

ring. Setting the BCR bit to 0 allows the processor to con-

tinue operations. Setting the BCR bit to 1 causes the

processor to stop execution while the BDMA accesses are

occurring, to clear the context of the processor, and start

execution at address 0 when the BDMA accesses have

completed.

The BDMA overlay bits specify the OVLAY memory blocks

to be accessed for internal memory. Set these bits as indi-

cated in.

Note: BDMA cannot access external overlay memory

regions 1 and 2.

The BMWAIT field, which has four bits on ADSP-218xN

series members, allows selection up to 15 wait states for

BDMA transfers.

Internal Memory DMA Port (IDMA Port; Host Memory

Mode)

The IDMA Port provides an efficient means of communi-

cation between a host system and ADSP-218xN series

members. The port is used to access the on-chip program

memory and data memory of the DSP with only one DSP

cycle per word overhead. The IDMA port cannot, however,

be used to write to the DSP’s memory-mapped control reg-

isters. A typical IDMA transfer process is shown as follows:

1. Host starts IDMA transfer.

2. Host checks IACK control line to see if the DSP is

busy.

3. Host uses IS and IAL control lines to latch either the

DMA starting address (IDMAA) or the PM/DM

OVLAY selection into the DSP’s IDMA control regis-

ters. If Bit 15 = 1, the value of bits 7–0 represent the

IDMA overlay; bits 14–8 must be set to 0. If Bit 15 = 0,

the value of Bits 13–0 represent the starting address

of internal memory to be accessed and Bit 14 reflects

PM or DM for access. Set IDDMOVLAY and

IDPMOVLAY bits in the IDMA overlay register as

indicted in Table 12.

4. Host uses IS and IRD (or IWR) to read (or write) DSP

internal memory (PM or DM).

5. Host checks IACK line to see if the DSP has completed

the previous IDMA operation.

6. Host ends IDMA transfer.

Table 12. IDMA/BDMA Overlay Bits

Processor

ADSP-2184N

ADSP-2185N

ADSP-2186N

ADSP-2187N

ADSP-2188N

ADSP-2189N

IDMA/BDMA

PMOVLAY

0

0

0

0, 4, 5

0, 4, 5, 6, 7

0, 4, 5

IDMA/BDMA

DMOVLAY

0

0

0

0, 4, 5

0, 4, 5, 6, 7, 8

0, 4, 5, 6, 7

The IDMA port has a 16-bit multiplexed address and data

bus and supports 24-bit program memory. The IDMA port

is completely asynchronous and can be written while the

ADSP-218xN is operating at full speed.

The DSP memory address is latched and then automatically

incremented after each IDMA transaction. An external

device can therefore access a block of sequentially addressed

memory by specifying only the starting address of the block.

This increases throughput as the address does not have to

be sent for each memory access.

IDMA Port access occurs in two phases. The first is the

IDMA Address Latch cycle. When the acknowledge is as-

serted, a 14-bit address and 1-bit destination type can be

driven onto the bus by an external device. The address spec-

ifies an on-chip memory location, the destination type spec-

ifies whether it is a DM or PM access. The falling edge of

the IDMA address latch signal (IAL) or the missing edge of

the IDMA select signal (IS) latches this value into the

IDMAA register.

Once the address is stored, data can be read from, or written

to, the ADSP-218xN’s on-chip memory. Asserting the

select line (IS) and the appropriate read or write line (IRD

and IWR respectively) signals the ADSP-218xN that a par-

ticular transaction is required. In either case, there is a one-

processor-cycle delay for synchronization. The memory

access consumes one additional processor cycle.

Once an access has occurred, the latched address is auto-

matically incremented, and another access can occur.

Through the IDMAA register, the DSP can also specify the

starting address and data format for DMA operation.

Asserting the IDMA port select (IS) and address latch

enable (IAL) directs the ADSP-218xN to write the address

onto the IAD14–0 bus into the IDMA Control Register

(Figure 13). If Bit 15 is set to 0, IDMA latches the address.

If Bit 15 is set to 1, IDMA latches into the OVLAY register.

This register, also shown in Figure 13, is memory-mapped

at address DM (0x3FE0). Note that the latched address

(IDMAA) cannot be read back by the host.

When Bit 14 in 0x3FE7 is set to zero, short reads use the

timing shown in Figure 34 on page 37. When Bit 14 in

0x3FE7 is set to 1, timing in Figure 35 on page 38 applies

for short reads in short read only mode. Set IDDMOVLAY

REV. 0

–17–

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