ADP3333ARM-1.8-RL7 View Datasheet(PDF) - Analog Devices
Part Name
Description
Manufacturer
ADP3333ARM-1.8-RL7 Datasheet PDF : 12 Pages
| |||
ADP3333
APPLICATIONS INFORMATION
CAPACITOR SELECTION
Output Capacitor
The stability and transient response of the LDO is a function of
the output capacitor. The ADP3333 is stable with a wide range
of capacitor values, types, and ESR (anyCAP). A capacitor as
low as 1.0 μF is all that is needed for stability. Larger capacitors
can be used if high current surges on the output are anticipated.
The ADP3333 is stable with extremely low ESR capacitors (ESR
≈ 0), such as multilayer ceramic capacitors (MLCC) or OSCON.
Note that the effective capacitance of some capacitor types falls
below the minimum rated value over temperature or with dc
voltage. Ensure that the capacitor provides at least 1.0 μF of
capacitance over temperature and dc bias.
Input Bypass Capacitor
An input bypass capacitor is not strictly required but is recom-
mended in any application involving long input wires or high
source impedance. Connecting a 1.0 μF capacitor from the input to
ground reduces the circuit’s sensitivity to printed circuit board
(PCB) layout and input transients. If a larger output capacitor is
necessary, then a larger value input capacitor is also recommended.
OUTPUT CURRENT LIMIT
The ADP3333 is short-circuit protected by limiting the pass
transistor’s base drive current. The maximum output current is
limited to about 1 A (see Figure 17).
THERMAL OVERLOAD PROTECTION
The ADP3333 is protected against damage due to excessive power
dissipation by its thermal overload protection circuit. Thermal
protection limits the die temperature to a maximum of 165°C.
Under extreme conditions (that is, high ambient temperature and
power dissipation) where the die temperature starts to rise above
165°C, the output current is reduced until the die temperature
drops to a safe level.
Current and thermal limit protections are intended to protect
the device against accidental overload conditions. For normal
operation, the device’s power dissipation should be externally
limited so that the junction temperature does not exceed 125°C.
CALCULATING JUNCTION TEMPERATURE
Device power dissipation is calculated as follows:
PD = (VIN − VOUT) IL + (VIN) IGND
where IL and IGND are the load current and ground current, and
VIN and VOUT are the input and output voltages, respectively.
Assuming the worst-case operating conditions are IL = 300 mA,
IGND = 2.0 mA, VIN = 4.0 V, and VOUT = 3.0 V, the device power
dissipation is
PD = (4.0 V − 3.0 V) 300 mA + (4.0 V) 2.0 mA = 308 mW
The package used on the ADP3333 has a thermal resistance of
158°C/W for 4-layer boards. The junction temperature rise
above ambient is approximately equal to
TJA = 0.308 W × 158°C/W = 48.7°C
Therefore, to limit the junction temperature to 125°C, the
maximum allowable ambient temperature is
TA(MAX) = 125°C − 48.7°C = 76.3°C
SHUTDOWN MODE
Applying a high signal to the shutdown pin, SD, or connecting
it to the input pin, IN, turns the output on. Pulling the shutdown
pin to 0.3 V or below, or connecting it to ground, turns the
output off. In shutdown mode, the quiescent current is reduced
to less than 1 μA.
PCB LAYOUT CONSIDERATIONS
Use the following general guidelines when designing printed
circuit boards:
Keep the output capacitor as close as possible to the output
and ground pins.
Keep the input capacitor as close as possible to the input
and ground pins.
PCB traces with larger cross sectional areas remove more
heat from the ADP3333. For optimum heat transfer, use
thick copper with wide traces.
Connect the NC pins (Pin 4, Pin 5, Pin 6, and Pin 8) to
ground for better thermal performance.
The thermal resistance can be decreased by approximately
10% by adding a few square centimeters of copper area to
the lands connected to the pins of the LDO.
Use additional copper layers or planes to reduce the
thermal resistance. Again, connecting the other layers to
the GND and NC pins of the ADP3333 is best, but not
necessary. When connecting the ground pad to other
layers, use multiple vias.
Rev. B | Page 10 of 12
|
|
Share Link: 