AD7244JRZ View Datasheet(PDF) - Analog Devices

Part Name

Description

Manufacturer

AD7244JRZ

LC2MOS Dual, Complete, 12-Bit/14-Bit Serial DACs

Analog Devices 

AD7242

DIP

Pin No.

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

AD7242/AD7244 PIN FUNCTION DESCRIPTION

Mnemonic Description

LDACA

Load DAC, Logic Input. A new word is transferred into DAC Latch A from input Latch A on the fall-

ing edge of this signal. If LDACA is hard-wired low, data is transferred from input Latch A to DAC

Latch A on the sixteenth falling edge of TCLKA after TFSA goes low.

TFSA

Transmit Frame Synchronization, Logic Input. This is a frame or synchronization signal for DACA

data with serial data expected after the falling edge of this signal.

DTA

Transmit Data, Logic Input. This is the data input which is used in conjunction with TFSA and

TCLKA to transfer serial data to input Latch A.

TCLKA

Transmit Clock, Logic Input. Serial data bits for DACA are latched on the falling edge of TCLKA

DGND

TP1

VDD

AGND

E VOUTB

VSS

T TP2

REF INB

E LDACB

L TFSB

DTB

TCLKB

O DGND

TP3

S VDD

AGND

VOUTA

B VSS

REF OUT

O REF INA

when TFSA is low.

Digital Ground. Both DGND pins for the device must be tied together at the device.

Test Pin 1. Used when testing the device. Do not connect anything to this pin.

Positive Power Supply, 5 V ± 5%. Both VDD pins for the device must be tied together at the device.

Analog Ground. Both AGND pins for the device must be tied together at the device.

Analog Output Voltage from DACB. This output comes from a buffer amplifier. The range is bipolar,

± 3 V with REF INB = +3 V.

Negative Power Supply, –5 V ± 5%. Both VSS pins for the device must be tied together at the device.

Test Pin 2. Used when testing the device. Do not connect anything to this pin.

DACB Voltage Reference Input. The voltage reference for DACB is applied to this pin. It is internally

buffered before being applied to DACB. The nominal reference voltage for correct operation of the

AD7242/AD7244 is 3 V.

Load DAC, Logic Input. A new word is transferred into DAC Latch B from input Latch B on the fall-

ing edge of this signal. If LDACB is hard-wired low, data is transferred from input Latch B to DAC

Latch B on the sixteenth falling edge of TCLKB after TFSB goes low.

Transmit Frame Synchronization, Logic Input. This is a frame or synchronization signal for DACB

data with serial data expected after the falling edge of this signal.

Transmit Data, Logic Input. This is the data input used in conjunction with TFSB and TCLKB to

transfer serial data to input Latch B.

Transmit Clock, Logic Input. Serial data bits for DACB are latched on the falling edge of TCLKB

when TFSB is low.

Digital Ground. Both DGND pins for the device must be tied together at the device.

Test Pin 3. Used when testing the device. Do not connect anything to this pin.

Positive Power Supply, 5 V ± 5%. Both VDD pins for the device must be tied together at the device.

Analog Ground. Both AGND pins for the device must be tied together at the device.

Analog Output Voltage from DACA. This output comes from a buffer amplifier. The range is bipolar,

± 3 V with REF INA = +3 V.

Negative Power Supply, –5 V ± 5%. Both VSS pins for the device must be tied together at the device.

Voltage Reference Output. To operate the DACs with this internal reference, REF OUT should be

connected to both REF INA and REF INB. The external load capability of the reference is 500 μA.

DACA Voltage Reference Input. The voltage reference for DACA is applied to this pin. It is internally

buffered before being applied to DACA. The nominal reference voltage for correct operation of the

AD7242/AD7244 is 3 V.

REV. B

–5–

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