AD6657A View Datasheet(PDF) - Analog Devices

Part Name

Description

Manufacturer

AD6657A

Quad IF Receiver

Analog Devices 

AD6657A

MEMORY MAP

READING THE MEMORY MAP REGISTER TABLE

Each row in the memory map register table has eight bit loca-

tions (see Table 13). The memory map is roughly divided into

four sections: the chip configuration registers (Address 0x00

and Address 0x01); the channel index and transfer registers

(Address 0x05 and Address 0xFF); the ADC function registers,

including setup, control, and test (Address 0x08 to Address 0x25);

and the digital feature control registers (Address 0x3A to

Address 0x3E).

The memory map register table (see Table 13) provides the

default hexadecimal value for each hexadecimal address shown.

The column with the heading (MSB) Bit 7 is the start of the

default hexadecimal value given. The AN-877 Application Note,

Interfacing to High Speed ADCs via SPI, documents the functions

controlled by Register 0x00 to Register 0xFF. The remaining

registers, Register 0x3A to Register 0x3E, are documented in

the Memory Map Register Descriptions section.

Open Locations

All address and bit locations that are not included in Table 13 are

not currently supported for this device. Unused bits of a valid

address location should be written with 0s. Writing to these

locations is required only when part of an address location is

open (for example, Address 0x18). If the entire address location

is open (for example, Address 0x13), this address location should

not be written.

Default Values

After the AD6657A is reset, critical registers are loaded with

default values. The default values for the registers are given in

the memory map register table (see Table 13).

Data Sheet

Logic Levels

An explanation of logic level terminology follows:

• “Bit is set” is synonymous with “bit is set to Logic 1” or

“writing Logic 1 for the bit.”

• “Clear a bit” is synonymous with “bit is set to Logic 0” or

“writing Logic 0 for the bit.”

Transfer Register Map

Address 0x08 to Address 0x3E are shadowed. Writes to these

addresses do not affect part operation until a transfer command

is issued by writing 0x01 to Address 0xFF, thereby setting the

transfer bit. This allows these registers to be updated internally

and simultaneously when the transfer bit is set. The transfer bit

is autoclearing.

Channel Specific Registers

Some channel setup functions, such as the NSR control func-

tion, can be programmed differently for each channel. In these

cases, channel address locations are internally duplicated for

each channel. These registers and bits are designated in Table 13

as local. Local registers and bits can be accessed by setting the

appropriate channel bits in Register 0x05.

If multiple channel bits are set, the subsequent write affects the

registers of all selected channels. In a read cycle, select a single

channel only to read one of the registers. If multiple channels are

selected during a SPI read cycle, the device returns the value for

Channel A only. Registers and bits designated as global in Table 13

affect the entire device or the channel features for which there are

no independent per channel settings. The settings in Register 0x05

do not affect the global registers and bits.

Rev. A | Page 30 of 36

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