ACS8526 查看數據表（PDF） - Semtech Corporation
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ACS8526 Datasheet PDF : 74 Pages
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ACS8526 LC/P LITE
ADVANCED COMMUNICATIONS
Address (hex): 6A (cont...)
Register Name cnfg_DPLL2_damping
FINAL
DATASHEET
Description
(R/W) Register to configure the
damping factor of DPLL2, along
with the gain of Phase Detector 2
in some modes.
Default Value
0001 0011
Bit 7
Bit 6
Bit 5
DPLL2_PD2_gain_alog
Bit 4
Bit 3
Bit 2
Bit 1
DPLL2_damping
Bit 0
Bit No.
Description
Bit Value Value Description
[2:0]
DPLL2_damping
Register to configure the damping factor of DPLL2.
The bit values correspond to different damping
factors, depending on the bandwidth selected.
The Gain Peak for the Damping Factors given in the
Value Description (right) are tabulated below:
Damping Factor
1.2
2.5
5
10
20
Gain Peak
0.4 dB
0.2 dB
0.1 dB
0.06 dB
0.03 dB
Damping Factor Damping Factor Damping Factor
for Bandwidth for Bandwidth for Bandwidth
of 18 Hz:
of 35 Hz:
of 70 Hz:
001
1.2
1.2
1.2
010
2.5
2.5
2.5
011
5
5
5
100
5
10
10
101
5
10
20
Address (hex): 6B
Register Name cnfg_DPLL1_damping
Description
(R/W) Register to configure the
damping factor of DPLL1, along
with the gain of the Phase
Detector 2 in some modes.
Default Value
0001 0100
Bit 7
Bit 6
Bit 5
Bit 4
DPLL1_PD2_gain_alog_8k
Bit 3
Bit 2
Bit 1
DPLL1_damping
Bit 0
Bit No.
Description
Bit Value Value Description
7
[6:4]
3
Not used.
DPLL1_PD2_gain_alog_8k
Register to control the gain of the Phase Detector 2
when locking to a reference of 8 kHz or less in
analog feedback mode. This setting is only used if
automatic gain selection is enabled in Reg. 6D Bit 7,
cnfg_DPLL1_PD2_gain.
Not used.
-
-
-
Gain value of the Phase Detector 2 when locking to
an 8 kHz reference in analog feedback mode.
-
-
Revision 4.01/June 2006 © Semtech Corp.
Page 52
www.semtech.com
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