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5962F9671001VXC View Datasheet(PDF) - Intersil

Part Name
Description
Manufacturer
5962F9671001VXC Datasheet PDF : 3 Pages
1 2 3
ACS541MS
January 1996
Radiation Hardened Octal Buffer/
Line Driver Three-State
Features
Pinouts
• Devices QML Qualified in Accordance with MIL-PRF-38535
• Detailed Electrical and Screening Requirements are Contained in
SMD# 5962-96710 and Intersil’s QM Plan
• 1.25 Micron Radiation Hardened SOS CMOS
• Total Dose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >300K RAD (Si)
• Single Event Upset (SEU) Immunity: <1 x 10-10 Errors/Bit/Day
(Typ)
• SEU LET Threshold . . . . . . . . . . . . . . . . . . . . . . . >100 MEV-cm2/mg
• Dose Rate Upset . . . . . . . . . . . . . . . . >1011 RAD (Si)/s, 20ns Pulse
• Dose Rate Survivability . . . . . . . . . . . >1012 RAD (Si)/s, 20ns Pulse
• Latch-Up Free Under Any Conditions
• Military Temperature Range . . . . . . . . . . . . . . . . . . -55oC to +125oC
• Significant Power Reduction Compared to ALSTTL Logic
• DC Operating Voltage Range . . . . . . . . . . . . . . . . . . . . 4.5V to 5.5V
• Input Logic Levels
- VIL = 30% of VCC Max
- VIH = 70% of VCC Min
• Input Current 1µA at VOL, VOH
• Fast Propagation Delay . . . . . . . . . . . . . . . . 17ns (Max), 12ns (Typ)
20 LEAD CERAMIC DUAL-IN-LINE
MIL-STD-1835 DESIGNATOR,
CDIP2-T20, LEAD FINISH C
TOP VIEW
OE1 1
A0 2
A1 3
A2 4
A3 5
A4 6
A5 7
A6 8
A7 9
GND 10
20 VCC
19 OE2
18 Y0
17 Y1
16 Y2
15 Y3
14 Y4
13 Y5
12 Y6
11 Y7
20 LEAD CERAMIC FLATPACK
MIL-STD-1835 DESIGNATOR,
CDFP4-F20, LEAD FINISH C
TOP VIEW
Description
OE1
1
A0
2
The Intersil ACS541MS is a Radiation Hardened Octal Buffer/Line
Driver, with three-state outputs. The output enable pins OE1, OE2 con-
A1
3
trol the Three-State outputs. If either enable is high the output will be in a
A2
4
high impedance state. For data output both enables must be low.
A3
5
A4
6
The ACS541MS utilizes advanced CMOS/SOS technology to achieve
A5
7
high-speed operation. This device is a member of a radiation hardened,
A6
8
high-speed, CMOS/SOS Logic family.
A7
9
The ACS541MS is supplied in a 20 lead Ceramic Flatpack (K suffix) or a
GND
10
Ceramic Dual-In-Line package (D suffix).
20
VCC
19
OE2
18
Y0
17
Y1
16
Y2
15
Y3
14
Y4
13
Y5
12
Y6
11
Y7
Ordering Information
PART NUMBER
5962F9671001VRC
5962F9671001VXC
ACS541D/Sample
ACS541K/Sample
ACS541HMSR
TEMPERATURE RANGE
-55oC to +125oC
-55oC to +125oC
25oC
25oC
25oC
SCREENING LEVEL
MIL-PRF-38535 Class V
MIL-PRF-38535 Class V
Sample
Sample
Die
PACKAGE
20 Lead SBDIP
20 Lead Ceramic Flatpack
20 Lead SBDIP
20 Lead Ceramic Flatpack
Die
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
1
Spec Number 518856
File Number 4085
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