A14100A Timing Characteristics
(Worst-Case Military Conditions, VCC = 4.5V, TJ = 125°C)
‘–1’ Speed
‘Std’ Speed
Parameter
Description
Logic Module Propagation Delays1
Min.
Max.
Min.
Max.
Units
tPD
Internal Array Module
tCO
Sequential Clock to Q
tCLR
Asynchronous Clear to Q
Logic Module Predicted Routing Delays2
3.0
3.5
ns
3.0
3.5
ns
3.0
3.5
ns
tRD1
FO=1 Routing Delay
tRD2
FO=2 Routing Delay
tRD3
FO=3 Routing Delay
tRD4
FO=4 Routing Delay
tRD8
FO=8 Routing Delay
Logic Module Sequential Timing
1.3
1.5
ns
1.9
2.1
ns
2.1
2.5
ns
2.6
2.9
ns
4.2
4.9
ns
tSUD
Flip-Flop (Latch) Data Input Setup
tHD
Flip-Flop (Latch) Data Input Hold
tSUENA
Flip-Flop (Latch) Enable Setup
tHENA
Flip-Flop (Latch) Enable Hold
tWASYN
Asynchronous Pulse Width
tWCLKA
Flip-Flop Clock Pulse Width
tA
Flip-Flop Clock Input Period
fMAX
Flip-Flop Clock Frequency
Input Module Propagation Delays
1.0
1.0
ns
0.6
0.6
ns
1.0
1.0
ns
0.6
0.6
ns
4.8
5.6
ns
4.8
5.6
ns
9.9
11.6
ns
100
85
MHz
tINY
Input Data Pad to Y
tICKY
Input Reg IOCLK Pad to Y
tOCKY
Output Reg IOCLK Pad to Y
tICLRY
Input Asynchronous Clear to Y
tOCLRY
Output Asynchronous Clear to Y
Input Module Predicted Routing Delays2, 3
4.2
4.9
ns
7.0
8.2
ns
7.0
8.2
ns
7.0
8.2
ns
7.0
8.2
ns
tIRD1
FO=1 Routing Delay
1.3
1.5
ns
tIRD2
FO=2 Routing Delay
1.9
2.1
ns
tIRD3
FO=3 Routing Delay
2.1
2.5
ns
tIRD4
FO=4 Routing Delay
2.6
2.9
ns
tIRD8
FO=8 Routing Delay
4.2
4.9
ns
Notes:
1. For dual-module macros, use tPD + tRD1 + tPDn , tCO + tRD1 + tPDn , or tPD1 + tRD1 + tSUD , whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device
performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is
based on actual routing delay measurements performed on the device prior to shipment.
3. Optimization techniques may further reduce delays by 0 to 4 ns.
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