A1460A Timing Characteristics (continued)
(Worst-Case Military Conditions, VCC = 4.5V, TJ = 125°C)
‘–1’ Speed
‘Std’ Speed
Parameter
Description
CMOS Output Module Timing1
Min.
Max.
Min.
Max.
Units
tDHS
Data to Pad, High Slew
tDLS
Data to Pad, Low Slew
tENZHS
Enable to Pad, Z to H/L, High Slew
tENZLS
Enable to Pad, Z to H/L, Low Slew
tENHSZ
Enable to Pad, H/L to Z, High Slew
tENLSZ
Enable to Pad, H/L to Z, Low Slew
tCKHS
IOCLK Pad to Pad H/L, High Slew
tCKLS
IOCLK Pad to Pad H/L, Low Slew
dTLHHS
Delta Low to High, High Slew
dTLHLS
Delta Low to High, Low Slew
dTHLHS
Delta High to Low, High Slew
dTHLLS
Delta High to Low, Low Slew
Dedicated (Hard-Wired) I/O Clock Network
9.2
10.8
ns
17.3
20.3
ns
7.7
9.1
ns
13.1
15.5
ns
10.9
12.8
ns
10.9
12.8
ns
14.1
16.0
ns
20.2
22.4
ns
0.06
0.07
ns/pF
0.11
0.13
ns/pF
0.04
0.05
ns/pF
0.05
0.06
ns/pF
tIOCKH
Input Low to High
(Pad to I/O Module Input)
3.5
4.1
ns
tIOPWH
Minimum Pulse Width High
tIOPWL
Minimum Pulse Width Low
tIOSAPW
Minimum Asynchronous Pulse Width
tIOCKSW
Maximum Skew
tIOP
Minimum Period
fIOMAX
Maximum Frequency
Dedicated (Hard-Wired) Array Clock Network
4.8
5.7
ns
4.8
5.7
ns
3.9
4.4
ns
0.9
1.0
ns
9.9
11.6
ns
100
85
MHz
tHCKH
Input Low to High
(Pad to S-Module Input)
5.5
6.4
ns
tHCKL
Input High to Low
(Pad to S-Module Input)
5.5
6.4
ns
tHPWH
Minimum Pulse Width High
4.8
5.7
ns
tHPWL
Minimum Pulse Width Low
4.8
5.7
ns
tHCKSW
Maximum Skew
0.9
1.0
ns
tHP
Minimum Period
9.9
11.6
ns
fHMAX
Maximum Frequency
100
85
MHz
Notes:
1. Delays based on 35 pF loading.
2. SSO information can be found in the Simultaneously Switching Output Limits for Actel FPGAs application note at
http://www.actel.com/appnotes.
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