A1425A Timing Characteristics (continued)
(Worst-Case Military Conditions, VCC = 4.5V, TJ = 125°C)
‘–1’ Speed
Parameter Description
Min.
Max.
I/O Module Sequential Timing
tINH
Input F-F Data Hold
(w.r.t. IOCLK Pad)
0.0
tINSU
Input F-F Data Setup
(w.r.t. IOCLK Pad)
2.1
tIDEH
Input Data Enable Hold
(w.r.t. IOCLK Pad)
0.0
tIDESU
Input Data Enable Setup
(w.r.t. IOCLK Pad)
8.7
tOUTH
Output F-F Data Hold
(w.r.t. IOCLK Pad)
1.1
tOUTSU
Output F-F Data Setup
(w.r.t. IOCLK Pad)
1.1
tODEH
Output Data Enable Hold
(w.r.t. IOCLK Pad)
0.5
tODESU
Output Data Enable Setup
(w.r.t. IOCLK Pad)
2.0
TTL Output Module Timing1
tDHS
Data to Pad, High Slew
tDLS
Data to Pad, Low Slew
tENZHS
Enable to Pad, Z to H/L, High Slew
tENZLS
Enable to Pad, Z to H/L, Low Slew
tENHSZ
Enable to Pad, H/L to Z, High Slew
tENLSZ
Enable to Pad, H/L to Z, Low Slew
tCKHS
IOCLK Pad to Pad H/L, High Slew
tCKLS
IOCLK Pad to Pad H/L, Low Slew
dTLHHS
Delta Low to High, High Slew
dTLHLS
Delta Low to High, Low Slew
dTHLHS
Delta High to Low, High Slew
dTHLLS
Delta High to Low, Low Slew
Note:
1. Delays based on 35 pF loading.
7.5
11.9
6.0
10.9
9.9
9.9
10.5
15.7
0.04
0.07
0.05
0.07
HiRel FPGAs
‘Std’ Speed
Min.
Max.
Units
0.0
ns
2.4
ns
0.0
ns
10.0
ns
1.2
ns
1.2
ns
0.6
ns
2.4
ns
8.9
ns
14.0
ns
7.0
ns
12.8
ns
11.6
ns
11.6
ns
11.6
ns
17.4
ns
0.04
ns/pF
0.08
ns/pF
0.06
ns/pF
0.08
ns/pF
37