5962-9952701QXC View Datasheet(PDF) - Actel Corporation
Part Name
Description
Manufacturer
5962-9952701QXC Datasheet PDF : 98 Pages
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ACT 1 Timing Characteristics (continued)
(Worst-Case Military Conditions, VCC = 4.5V, TJ = 125°C)
‘–1’ Speed
‘Std’ Speed
Parameter Description
Min.
Max.
Min.
Max. Units
Global Clock Network
tCKH
Input Low to High
tCKL
Input High to Low
tPWH
Minimum Pulse Width High
tPWL
Minimum Pulse Width Low
tCKSW
Maximum Skew
tP
Minimum Period
fMAX
Maximum Frequency
TTL Output Module Timing1
FO = 16
FO = 128
FO = 16
FO = 128
FO = 16
FO = 128
FO = 16
FO = 128
FO = 16
FO = 128
FO = 16
FO = 128
FO = 16
FO = 128
10.4
10.9
10.4
10.9
21.7
23.2
7.8
8.9
10.3
11.2
1.9
2.9
46
44
12.2
12.9
12.2
12.9
25.6
27.3
9.2
10.5
ns
12.1
13.2
ns
ns
ns
2.2
3.4
ns
ns
40
37
MHz
tDLH
Data to Pad High
tDHL
Data to Pad Low
tENZH
Enable Pad Z to High
tENZL
Enable Pad Z to Low
tENHZ
Enable Pad High to Z
tENLZ
Enable Pad Low to Z
dTLH
Delta Low to High
dTHL
Delta High to Low
CMOS Output Module Timing1
12.1
14.2
ns
13.8
16.3
ns
12.0
14.1
ns
14.6
17.1
ns
16.0
18.8
ns
14.5
17.0
ns
0.09
0.11
ns/pF
0.12
0.15
ns/pF
tDLH
Data to Pad High
15.1
17.7
ns
tDHL
Data to Pad Low
11.5
13.6
ns
tENZH
Enable Pad Z to High
12.0
14.1
ns
tENZL
Enable Pad Z to Low
14.6
17.1
ns
tENHZ
Enable Pad High to Z
16.0
18.8
ns
tENLZ
Enable Pad Low to Z
14.5
17.0
ns
dTLH
Delta Low to High
0.16
0.18
ns/pF
dTHL
Delta High to Low
0.09
0.11
ns/pF
Notes:
1. Delays based on 50 pF loading.
2. SSO information can be found in the Simultaneously Switching Output Limits for Actel FPGAs application note at
http://www.actel.com/appnotes.
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