5962-9952701QXC View Datasheet(PDF) - Actel Corporation
Part Name
Description
Manufacturer
5962-9952701QXC Datasheet PDF : 98 Pages
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HiRel FPGAs
ACT 1 Timing Characteristics
(Worst-Case Military Conditions, VCC = 4.5V, TJ = 125°C)
‘–1’ Speed
‘Std’ Speed
Parameter
Description
Min.
Max.
Min.
Max.
Units
Logic Module Propagation Delays
tPD1
Single Module
tPD2
Dual Module Macros
tCO
Sequential Clk to Q
tGO
Latch G to Q
tRS
Flip-Flop (Latch) Reset to Q
Logic Module Predicted Routing Delays1
4.7
5.5
ns
10.8
12.7
ns
4.7
5.5
ns
4.7
5.5
ns
4.7
5.5
ns
tRD1
FO=1 Routing Delay
tRD2
FO=2 Routing Delay
tRD3
FO=3 Routing Delay
tRD4
FO=4 Routing Delay
tRD8
FO=8 Routing Delay
Logic Module Sequential Timing 2
1.5
1.7
ns
2.3
2.7
ns
3.4
4.0
ns
5.0
5.9
ns
10.6
12.5
ns
tSUD
tHD
tSUENA
tHENA
tWCLKA
tWASYN
tA
fMAX
Flip-Flop (Latch) Data Input Setup
8.8
10.4
ns
Flip-Flop (Latch) Data Input Hold
0.0
0.0
ns
Flip-Flop (Latch) Enable Setup
8.8
10.4
ns
Flip-Flop (Latch) Enable Hold
0.0
0.0
ns
Flip-Flop (Latch) Clock Active Pulse
Width
10.9
12.9
ns
Flip-Flop (Latch) Asynchronous Pulse
Width
10.9
12.9
ns
Flip-Flop Clock Input Period
23.2
27.3
ns
Flip-Flop (Latch) Clock
Frequency
44
37
MHz
Input Module Propagation Delays
tINYH
Pad to Y High
4.9
5.8
ns
tINYL
Pad to Y Low
Input Module Predicted Routing Delays1, 3
4.9
5.8
ns
tIRD1
FO=1 Routing Delay
1.5
1.7
ns
tIRD2
FO=2 Routing Delay
2.3
2.7
ns
tIRD3
FO=3 Routing Delay
3.4
4.0
ns
tIRD4
tIRD8
FO=4 Routing Delay
FO=8 Routing Delay
5.0
5.9
ns
10.6
12.5
ns
Notes:
1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device
performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is based
on actual routing delay measurements performed on the device prior to shipment.
2. Setup times assume fanout of 3. Further derating information can be obtained from the DirectTime Analyzer utility.
3. Optimization techniques may further reduce delays by 0 to 4 ns.
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