PIC18F2220 View Datasheet(PDF) - Microchip Technology

Part Name

Description

Manufacturer

PIC18F2220

28/40/44-Pin High-Performance, Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology

Microchip Technology 

PIC18F2220/2320/4220/4320

3.3.2 SEC_IDLE MODE

In SEC_IDLE mode, the CPU is disabled but the

peripherals continue to be clocked from the Timer1

oscillator. This mode is entered by setting the IDLEN

bit, modifying to SCS1:SCS0 = 01 and executing a

SLEEP instruction. When the clock source is switched

to the Timer1 oscillator (see Figure 3-5), the primary

oscillator is shut down, the OSTS bit is cleared and the

T1RUN bit is set.

Note:

The Timer1 oscillator should already be

running prior to entering SEC_IDLE mode.

If the T1OSCEN bit is not set when try-

ing to set the SCS0 bit (OSCCON<0>),

the write to SCS0 will not occur. If the

Timer1 oscillator is enabled but not yet

running, peripheral clocks will be delayed

until the oscillator has started; in such sit-

uations, initial oscillator operation is far

from stable and unpredictable operation

may result.

When a wake-up event occurs, the peripherals continue

to be clocked from the Timer1 oscillator. After a 10 µs

delay following the wake-up event, the CPU begins exe-

cuting code, being clocked by the Timer1 oscillator. The

microcontroller operates in SEC_RUN mode until the

primary clock becomes ready. When the primary clock

becomes ready, a clock switch back to the primary clock

occurs (see Figure 3-6). When the clock switch is com-

plete, the T1RUN bit is cleared, the OSTS bit is set and

the primary clock is providing the system clock. The

IDLEN and SCS bits are not affected by the wake-up;

the Timer1 oscillator continues to run.

FIGURE 3-5:

TIMING TRANSITION FOR ENTRY TO SEC_IDLE MODE

Q1 Q2 Q3 Q4 Q1

T1OSI

OSC1

1

2

3

4

5

6

7

8

Clock Transition

CPU

Clock

Peripheral

Clock

Program

Counter

PC

PC + 2

FIGURE 3-6:

TIMING TRANSITION FOR WAKE FROM SEC_RUN MODE (HSPLL)

Q1

Q2

Q3

Q4 Q1

Q2 Q3 Q4 Q1 Q2 Q3

T1OSI

OSC1

PLL Clock

Output

TOST(1)

TPLL(1)

12345678

Clock Transition

CPU Clock

Peripheral

Clock

Program

Counter

PC

PC + 2

PC + 4

Wake-up from Interrupt Event

OSTS bit Set

Note 1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.

PC + 6

DS39599C-page 34

 2003 Microchip Technology Inc.

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