RC48F4P0ZBQ0 查看數據表（PDF） - Intel
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RC48F4P0ZBQ0 Datasheet PDF : 102 Pages
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1-Gbit P30 Family
Figure 47. Protection Register Programming Flowchart
PROTECTION REGISTER PROGRAMMING PROCEDURE
Start
Write 0xC0,
PR Address
(Program Setup)
Write PR
Address & Data (Confirm Data)
Bus
Operation
Command
Comments
Write
Program Data = 0xC0
PR Setup Addr = First Location to Program
Write
Protection Data = Data to Program
Program Addr = Location to Program
Read
None Status Register Data.
Read Status
Register
SR[7] =
0
1
Full Status
Check
(if desired)
Program
Complete
Check SR[7]:
Idle
None 1 = WSM Ready
0 = WSM Busy
Program Protection Register operation addresses must be
within the Protection Register address space. Addresses
outside this space will return an error.
Repeat for subsequent programming operations.
Full Status Register check can be done after each program, or
after a sequence of program operations.
Write 0xFF after the last operation to set Read Array state.
FULL STATUS CHECK PROCEDURE
Read Status
Register Data
SR[3] =
1
0
SR[4] =
1
0
SR[1] =
1
0
Program
Successful
VPP Range Error
Program Error
Register Locked;
Program Aborted
Bus
Operation
Command
Comments
Idle
None
Check SR[3]:
1 =VPP Range Error
Idle
None
Check SR[4]:
1 =Programming Error
Idle
None
Check SR[1]:
1 =Block locked; operation aborted
Only the Clear Staus Register command clears SR[1, 3, 4].
If an error is detected, clear the Status register before
attempting a program retry or other error recovery.
April 2005
92
Intel StrataFlash® Embedded Memory (P30)
Order Number: 306666, Revision: 001
Datasheet
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