A(18:0)
tAVAV
DQn(7:0)
Previous Valid Data
Assumptions:
1. En and G < VIL (max) and Wn > VIH (min)
tAXQX
Valid Data
tAVQV
Figure 3a. SRAM Read Cycle 1: Address Access
A(18:0)
En
DQn(7:0)
tETQX
tETQV
tEFQZ
DATA VALID
Assumptions:
1. G < VIL (max) and Wn > VIH (min)
Figure 3b. SRAM Read Cycle 2: Chip Enable-Controlled Access
A(18:0)
tAVQV
G
DQn(7:0)
Assumptions:
1. En < VIL (max) and Wn > VIH (min)
tGLQX
tGLQV
tGHQZ
DATA VALID
Figure 3c. SRAM Read Cycle 3: Output Enable-Controlled Access
7