XA-C3 View Datasheet(PDF) - Philips Electronics

Part Name

Description

Manufacturer

XA-C3

XA 16-bit microcontroller family 32K/1024 OTP CAN transport layer controller 1 UART, 1 SPI Port, CAN 2.0B, 32 CAN ID Filters, transport layer co-processor

Philips Electronics 

Philips Semiconductors

XA 16-bit microcontroller family

32K/1024 OTP CAN transport layer controller

1 UART, 1 SPI Port, CAN 2.0B, 32 CAN ID filters, transport layer co-processor

Preliminary specification

XA-C3

WATCHDOG FEED SEQUENCE

MOV WFEED1,#A5H

MOV WFEED2,#5AH

TCLK

PRESCALER

WDL

8–BIT DOWN

COUNTER

INTERNAL RESET

PRE2

PRE1

PRE0

—

—

WDRUN WDTOF

Figure 14. Watchdog Timer in XA-C3

—

WDCON

SU00581A

When the watchdog underflows, the following action takes place

(see Figure 14):

D Autoload takes place.

D Watchdog time–out flag is set

D Watchdog run bit unchanged.

D Autoload (WDL) register unchanged.

D Prescaler tap unchanged.

D All other device action same as External Reset.

Note that if the watchdog underflows, the Program counter will be

loaded from the Reset vector as in the case of an internal Reset.

The watchdog time–out flag can be examined to determine if the

watchdog has caused the Reset condition. The watchdog time–out

flag bit can be cleared by software.

WDCON Register Bit Definitions

WDCON[7] PRE2

Prescaler Select 2, Reset to 1

WDCON[6] PRE1

Prescaler Select 1, Reset to 1

WDCON[5] PRE0

Prescaler Select 0, Reset to 1

WDCON[2] WDRUN

Watchdog Run Control bit, Reset to 1

WDCON[1] WDTOF

Timeout flag

UART

The XA–C3 includes 1 UART port (UART–0) that is compatible with

the enhanced UART used on the 8xC51FB. Baud rate selection is

somewhat different due to the clocking scheme used for the XA

timers.

Four other enhancements have been made to UART operation:

First, there are separate interrupt vectors for UART transmit and

receive functions. Second, the UART–0 transmitter has been

double–buffered, allowing packed transmission of data with no gaps

between bytes and less critical interrupt service routine timing.

Third, a break detect function has been added to UART–0. This

operates independently of the UART and provides a start–of–break

status bit that the User program may use to test BR0 (S0STAT[2]).

Fourth, an Overrun Error flag has been added to detect missed

characters in the received data stream.

The UART baud rate is determined by either a fixed division of the

oscillator (in UART–0 Modes 0 and 2) or by the Timer 1 or Timer 2

overflow rate (in UART–0 Modes 1 and 3).

Timer 1 defaults to clock UART–0. Timer 2 can clock UART–0

through T2CON via bits RCLK0 (T2CON[5]) and/or TCLK0

(T2CON[4]).

The serial port receive and transmit registers are both accessed at

Special Function Register S0BUF. Writing to S0BUF loads the

transmit register, and reading S0BUF accesses the physically

separate receive register.

The serial port can operate in 4 modes:

Mode 0: Serial I/O expansion mode. Serial data enters and exits

through RxD. TxD outputs the shift clock. 8 bits are

transmitted/received (LSB first). (The baud rate is fixed at 1/16 the

oscillator frequency.)

Mode 1: Standard 8–bit UART mode. 10 bits are transmitted

(through TxD) or received (through RxD): a start bit (0), 8 data bits

(LSB first), and a stop bit (1). On receive, the stop bit goes into bit

RB8_0 (S0CON[2]). The baud rate is variable via Timer 1 or Timer 2

overflow rates.

Mode 2: Fixed rate 9–bit UART mode. 11 bits are transmitted

(through TxD) or received (through RxD): start bit (0), 8 data bits

(LSB first), a programmable 9th data bit, and a stop bit (1). On

Transmit, the 9th data bit TB8_0 (S0CON[3]) can be assigned the

value of 0 or 1. Or, for example, the parity bit (P, in the PSW) could

be moved into TB8_0. On receive, the 9th data bit goes into bit

RB8_0, while the stop bit is ignored. The baud rate is programmable

to 1/32 of the oscillator frequency.

Mode 3: Standard 9–bit UART mode. 11 bits are transmitted

(through TxD) or received (through RxD): a start bit (0), 8 data bits

(LSB first), a programmable 9th data bit, and a stop bit (1). In fact,

Mode 3 is the same as Mode 2 in all respects except baud rate. The

baud rate in Mode 3 is variable via Timer 1 or Timer 2 overflow

rates.

In all four modes, transmission is initiated by any instruction that

uses S0BUF as a destination register. Reception is initiated in Mode

0 by the condition RI_0 (S0CON[0]) = 0 AND REN_0 (S0CON[4]) =

2000 Jan 25

19

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