PXAC37KBA View Datasheet(PDF) - Philips Electronics

Part Name

Description

Manufacturer

PXAC37KBA

XA 16-bit microcontroller family 32K/1024 OTP CAN transport layer controller 1 UART, 1 SPI Port, CAN 2.0B, 32 CAN ID Filters, transport layer co-processor

Philips Electronics 

Philips Semiconductors

XA 16-bit microcontroller family

32K/1024 OTP CAN transport layer controller

1 UART, 1 SPI Port, CAN 2.0B, 32 CAN ID filters, transport layer co-processor

Preliminary specification

XA-C3

NAME

DESCRIPTION

S0STAT*

S0BUF

S0ADDR

S0ADEN

SCR

Serial port 0 extended status

Serial port 0 buffer register

Serial port 0 address register

Serial port 0 address enable

register

System configuration register

SSEL*

SWE

Segment selection register

Software Interrupt Enable

SWR*

Software Interrupt Request

T2CON* Timer 2 control register

T2MOD*

TH2

TL2

T2CAPH

T2CAPL

Timer 2 mode control

Timer 2 high byte

Timer 2 low byte

Timer 2 capture register, high

byte

Timer 2 capture register, low

byte

TCON*

TH0

TH1

TL0

TL1

TMOD

Timer 0 and 1 control register

Timer 0 high byte

Timer 1 high byte

Timer 0 low byte

Timer 1 low byte

Timer 0 and 1 mode control

TSTAT* Timer 0 and 1 extended status

WDCON*

WDL

WFEED1

WFEED2

Watchdog control register

Watchdog timer reload

Watchdog feed 1

Watchdog feed 2

SFR

ADDRESS

421h

460h

461h

462h

440h

403h

47Ah

42Ah

418h

419h

459h

458h

45Bh

7

30F

–

–

21F

ESWEN

–

357

–

2C7

TF2

2CF

–

BIT FUNCTIONS AND BIT ADDRESSES

6

5

4

3

2

1

30E

30D

30C

30B

30A

309

–

–

–

FE0

BR0

OE0

–

21E

R6SEG

SWE7

356

SWR7

2C6

EXF2

2CE

–

–

21D

R5SEG

SWE6

355

SWR6

2C5

RCLK0

2CD

–

–

21C

R4SEG

SWE5

354

SWR5

2C4

TCLK0

2CC

–

PT1

21B

R3SEG

SWE4

353

SWR4

2C3

EXEN2

2CB

–

PT0

21A

R2SEG

SWE3

352

SWR3

2C2

TR2

2CA

–

CM

219

R1SEG

SWE2

351

SWR2

2C1

C2 or

T2/

2C9

T2OE

RESET

0

308

STINT0

VALUE

00h

xxh

00h

00h

PZ 00h

218

R0SEG 00h

SWE1 00h

350

SWR1 00h

2C0

CP or

RL2/

00h

2C8

DCEN 00h

00h

00h

00h

45Ah

410h

451h

453h

450h

452h

45Ch

411h

41Fh

45Fh

45Dh

45Eh

287

286

285

TF1

TR1

TF0

GATE1

28F

–

2FF

PRE2

C1 or T1/

28E

–

2FE

PRE1

M1

28D

–

2FD

PRE0

00h

284

283

282

281

280

TR0

IE1

IT1

IE0

IT0 00h

00h

00h

00h

00h

M0

GATE0 C0 or T0/

M1

M0 00h

28C

28B

28A

289

288

–

–

T1OE

–

T0OE 00h

2FC

2FB

2FA

2F9

2F8

–

–

WDRUN WDTOF

–

Note 6

00h

xxh

xxh

NOTES:

1. Users should never write to the BCR register.

2. Users must ALWAYS INITIALIZE (Write) 00h to this register.

3. Port configurations default to Quasi–Bidirectional when the XA begins execution from Internal code memory after Reset, based on the

condition found on the EA/ pin. Thus, all PnCFGA registers will contain FFh and PnCFGB registers will contain 00h. When the XA begins

execution using External code memory, the default configuration for pins that are associated with the External bus will be Push–Pull. The

PnCFGA and PnCFGB register contents will reflect this difference.

4. SFR is loaded from the Reset vector.

5. All bits except F1, F0, and P are loaded from the Reset vector. Those bits are all 0.

6. The WDCON Reset value is E6h for a Watchdog Reset, E4h for all other Reset causes. The Watchdog is always turned ON as one

consequence of RST/. Therefore, the user should turn OFF the Watchdog if immediate Watchdog operation is not desired: See the

Watchdog Timer section in this Data Sheet for a recommended code example.

GENERAL NOTES:

– SFRs marked with an asterisk (*) are bit–addressable.

– The XA–C3 implements an 8–bit SFR bus, as stated in Chapter 8 of the XA User Guide. All SFR accesses must be 8–bit operations.

Attempts to write 16 bits to an SFR will actually write only the lower 8 bits. Sixteen–bit SFR reads will return undefined data in the upper byte.

– Unimplemented bits in SFRs (indicated by ”–”} are unknown at all times. Ones should not be written to these bits since they may be used for

other purposes in future XA derivatives. In general, the Reset value shown for these unimplemented bits is 00h.

– The XA guards writes to all SFR bits that can be modified by hardware, including all SFR resident interrupt flags, as well as the WDTOF bit in

WDCON. This mechanism, called Read–Modify–Write Lockout, prevents loss of an interrupt (or other status) flag if a bit is written to directly

by hardware between the read and write of an instruction that performs a read–modify–write operation.

2000 Jan 25

10

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