MTV312M View Datasheet(PDF) - Unspecified

Part Name

Description

Manufacturer

MTV312M

8051 Embedded Monitor Controller Flash Type with ISP

Unspecified 

MYSON

TECHNOLOGY

MTV312M64

(Rev 0.99)

10.4 ISP Data Read

The 1st and 2nd bytes are the same as “Data Write” to define the low address of Flash. Between 2nd and 3rd

bytes, the ISP host may issue Stop-Start or only Re-Start. From the 4th byte, the ISP slave sends the data

byte of Flash to ISP Host. The low address automatically increases every time when data byte is transferred.

10.5 Cyclic Redundancy Check (CRC)

To shorten the verify time, the ISP slave provides a simple way to check whether data error occurs during

the program data transfer. After the ISP Host sends a lot of data byte to ISP slave, Host can use Command

Read to check result of CRC register instead of reading every byte in Flash. The CRC register counts every

data byte which ISP slave acknowledges during “Data Write” period. However, the low address byte and the

data byte of Erase/Blank are not counted. The Clear CRC command will write all “1” to the 16-bit CRC

register. For CRC generation, the 16-bit CRC register is seeded with all “1” pattern (by device reset or Clear

CRC command). The data byte shifted into the CRC register is Msb first. The actual implementation is

described as follows:

CRCin = CRC[15]^DATAin;

CRC[15:0] = {CRC[14]^CRCin, CRC[13:2], CRC[1]^CRCin, CRC[0], CRCin};

Where ^ = XOR

example:

data_byte

F6H

28H

C3H

CRC_register_remainder

FFFFH

FF36H

34F2H

7031H

10.6 Reset Device

After the Flash been program completed and verified OK, the ISP Host can use “Command Write” with

Reset_CPU command to wake up MTV312M.

Reg name addr

bit7

bit6

bit5

bit4

bit3

bit2

bit1

bit0

ISPSLV F0Bh(w)

ISP Slave address

ISPEN F0Ch(w)

Write 93h to enable ISP Mode

Revision 0.99

- 21 -

2001/07/26

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