MTV312M View Datasheet(PDF) - Unspecified

Part Name

Description

Manufacturer

MTV312M

8051 Embedded Monitor Controller Flash Type with ISP

Unspecified 

MYSON

TECHNOLOGY

MTV312M64

(Rev 0.99)

EReStaI = 1

EWSlvAI = 1

EMbufI = 1

→ Enables IIC bus repeat START interrupt.

→ Enables slave A IIC bus STOP of write mode interrupt.

→ Enables Master IIC bus interrupt.

Mbuf (w) :

Master IIC data shift register, after START and before STOP condition, write this register

resumes MTV312M's transmission to the IIC bus.

Mbuf (r) :

Master IIC data shift register, after START and before STOP condition, read this register

resumes MTV312M's reception from the IIC bus.

DDCCTR (w) : DDC interface control register.

DDC1en = 1 → Enables DDC1 data transfer in DDC1 mode.

= 0 → Disables DDC1 data transfer in DDC1 mode.

En128W = 1 → The lower 128 bytes (00-7F) of DDCRAM can be written by IIC master.

= 0 → The lower 128 bytes (00-7F) of DDCRAM cannot be written by IIC master.

En256W = 1 → The higher 128 bytes (80-FF) of DDCRAM can be written by IIC master.

= 0 → The higher 128 bytes (80-FF) of DDCRAM cannot be written by IIC master.

Only128 = 1 → The SlaveA always accesses EDID data from the lower 128 bytes of DDCRAM.

= 0 → The SlaveA accesses EDID data from the whole 256 bytes DDCRAM.

SlvAbs1,SlvAbs0 : Slave IIC block A's slave address length.

= 1,0 → 5-bit slave address.

= 0,1 → 6-bit slave address.

= 0,0 → 7-bit slave address.

SLVAADR (w) : Slave IIC block A's enable and address.

ENslvA = 1 → Enables slave IIC block A.

= 0 → Disables slave IIC block A.

bit6-0 :

Slave IIC address A to which the slave block should respond.

RCBBUF (r) : Slave IIC block B receives data buffer.

TXBBUF (w) : Slave IIC block B transmits data buffer.

SLVBADR (w) : Slave IIC block B's enable and address.

ENslvB = 1 → Enables slave IIC block B.

= 0 → Disables slave IIC block B.

bit6-0 :

Slave IIC address B to which the slave block should respond.

8. Low Power Reset (LVR) & Watchdog Timer

When the voltage level of power supply is below 3.8V(+/-0.2V) / 2.5V(+/-0.15V) in 5V / 3.3V applications for

a specific period of time, the LVR generates a chip reset signal. After the power supply is above 3.8V(+/-

0.2V) / 2.5V(+/-0.15V) in 5V / 3.3V applications, LVR maintains in reset state for 144 X'tal cycle to guarantee

the chip exit reset condition with a stable X'tal oscillation.

The Watchdog Timer automatically generates a device reset when it is overflowed. The interval of overflow

is 0.25 sec x N, where N is a number from 1 to 8, and can be programmed via register WDT(2:0). The timer

function is disabled after power on reset, users can activate this function by setting WEN, and clear the timer

by setting WCLR.

9. A/D converter

The MTV312M is equipped with four VDD range 6-bit A/D converters. So if the VDD = 5V/3.3V, and then the

Revision 0.99

- 18 -

2001/07/26

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