MTV312M View Datasheet(PDF) - Unspecified

Part Name

Description

Manufacturer

MTV312M

8051 Embedded Monitor Controller Flash Type with ISP

Unspecified 

MYSON

TECHNOLOGY

MTV312M64

(Rev 0.99)

[(CLPW2:CLPW0) + 1] x 0.167 µs for 12MHz X’tal selection.

INTFLG (w) : Interrupt flag. An interrupt event will set its individual flag, and, if the corresponding interrupt

enable bit is set, the INT1 source of 8051 core will be driven by a zero level. Software

MUST clear this register while serving the interrupt routine.

HPRchg= 1 → No action.

= 0 → Clears HSYNC presence change flag.

VPRchg= 1 → No action.

= 0 → Clears VSYNC presence change flag.

HPLchg= 1 → No action.

= 0 → Clears HSYNC polarity change flag.

VPLchg = 1 → No action.

= 0 → Clears VSYNC polarity change flag.

HFchg = 1 → No action.

= 0 → Clears HSYNC frequency change flag.

VFchg = 1 → No action.

= 0 → Clears VSYNC frequency change flag.

Vsync = 1 → No action.

= 0 → Clears VSYNC interrupt flag.

INTFLG (r) : Interrupt flag.

HPRchg= 1 → Indicates a HSYNC presence change.

VPRchg= 1 → Indicates a VSYNC presence change.

HPLchg= 1 → Indicates a HSYNC polarity change.

VPLchg = 1 → Indicates a VSYNC polarity change.

HFchg = 1 → Indicates a HSYNC frequency change or counter overflow.

VFchg = 1 → Indicates a VSYNC frequency change or counter overflow.

Vsync = 1 → Indicates a VSYNC interrupt.

INTEN (w) : Interrupt enable.

EHPR = 1 → Enables HSYNC presence change interrupt.

EVPR = 1 → Enables VSYNC presence change interrupt.

EHPL = 1 → Enables HSYNC polarity change interrupt.

EVPL = 1 → Enables VSYNC polarity change interrupt.

EHF = 1 → Enables HSYNC frequency change / counter overflow interrupt.

EVF = 1 → Enables VSYNC frequency change / counter overflow interrupt.

EVsync = 1 → Enables VSYNC interrupt.

7. DDC & IIC Interface

7.1 DDC1/DDC2x Mode, DDCRAM and SlaveA block

The MTV312M enters DDC1 mode after Reset. In this mode, VSYNC is used as data clock. The HSCL pin

should remain at high. The data output to the HSDA pin is taken from a shift register in MTV312M. The shift

register automatically fetches EDID data from the lower 128 bytes of the Dual Port RAM (DDCRAM), then

sends it in 9-bit packet formats inclusive of a null bit (=1) as packet separator. S/W may enable/disable the

DDC1 function by setting/clearing the DDC1en control bit.

The MTV312M switches to DDC2x mode when it detects a high to low transition on the HSCL pin. In this

mode, the SlaveA IIC block automatically transmits/receives data to/from the IIC Master. The

transmitted/received data is taken-from/saved-to the DDCRAM. In simple words, MTV312M can behaves as

24LC02 EEPROM. The only thing S/W needs to do is to write the EDID data to DDCRAM. The slave

address of SlaveA block can be chosen by S/W as 5-bit, 6-bit or 7-bit. For example, if S/W chooses 5-bit

slave address as 10100b, the SlaveA IIC block then responds to slave address 10100xxb. The SlaveA can

be enabled/disabled by setting/clearing the EnslvA bit. The lower/upper DDCRAM can/cannot be written by

Revision 0.99

- 15 -

2001/07/26

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