MTV312M View Datasheet(PDF) - Unspecified
Part Name
Description
Manufacturer
MTV312M Datasheet PDF : 27 Pages
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MYSON
TECHNOLOGY
MTV312M64
(Rev 0.99)
= 0 → Off level of HSYNC input is low.
Voff* = 1 → Off level of VSYNC input is high.
= 0 → Off level of VSYNC input is low.
*Hoff and Voff are valid when Hpre=0 or Vpre=0.
HCNTH (r) : H-Freq counter's high bits.
Hovf = 1 → H-Freq counter is overflowed, this bit is cleared by H/W when condition removed.
HF13 - HF8 : 6 high bits of H-Freq counter.
HCNTL (r) : H-Freq counter's low byte.
VCNTH (r) : V-Freq counter's high bits.
Vovf = 1 → V-Freq counter is overflowed, this bit is cleared by H/W when condition removed.
VF11 - 8 :
4 high bits of V-Freq counter.
VCNTL (r) : V-Freq counter's low byte.
HVCTR0 (w) : H/V SYNC processor control register 0.
C1, C0 = 1,1 → Selects CVSYNC as the polarity, freq and VBLANK source.
= 1,0 → Selects VSYNC as the polarity, freq and VBLANK source.
= 0,0 → Disables composite function.
= 0,1 → H/W automatically switches to CVSYNC when CVpre=1 and VSpre=0.
NoHins = 1 → HBLANK has no insert pulse in composite mode.
= 0 → HBLANK has insert pulse in composite mode.
SelExH = 1 → Input source of HLFHO is HLFHI.
= 0 → Input source of HLFHO is HSYNC.
IVHlfH = 1 → HLFHO is inverted.
= 0 → HLFHO is not inverted.
HlfHE = 1 → HLFHO is half freq. of HSYNC/HLFHI.
= 0 → HLFHO is same freq. of HSYNC/HLFHI.
HBpl = 1 → Negative polarity HBLANK output.
= 0 → Positive polarity HBLANK output.
VBpl = 1 → Negative polarity VBLANK output.
= 0 → Positive polarity VBLANK output.
HVCTR2 (w) : Self-test pattern generator control.
Selft = 1 → Enables generator.
= 0 → Disables generator.
STF1, STF0 = 1,1 → 95.2KHz (horizontal) / 72Hz (vertical) output selected.
= 1,0 → 63.5KHz (horizontal) / 60Hz (vertical) output selected.
= 0,1 → 47.6KHz (horizontal) / 60Hz (vertical) output selected.
= 0,0 → 31.75KHz (horizontal) / 60Hz (vertical) output selected.
Rt1,Rt0 = 0,0 → Positive cross-hatch pattern output.
= 0,1 → Negative cross-hatch pattern output.
= 1,0 → Full white pattern output.
= 1,1 → Full black pattern output.
HVCTR3 (w) : HSYNC clamp pulse control register.
CLPEG = 1 → Clamp pulse follows HSYNC leading edge.
= 0 → Clamp pulse follows HSYNC trailing edge.
CLPPO = 1 → Positive polarity clamp pulse output.
= 0 → Negative polarity clamp pulse output.
CLPW2 : CLPW0 : Pulse width of clamp pulse is
Revision 0.99
- 14 -
2001/07/26
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