EP9307 View Datasheet(PDF) - Cirrus Logic

Part Name

Description

Manufacturer

EP9307

ARM9 SOC with Ethernet, USB, Display, and Touchscreen

Cirrus Logic 

Table O. General Purpose Input/Output Pin Assignment

Pin Mnemonic

Pin Name - Description

EGPIO[15]

EGPIO[13:0]

FGPIO[7]

FGPIO[5]

FGPIO[0]

Expanded General Purpose Input / Output

Pins with Interrupts

Expanded General Purpose Input / Output

Pins with Interrupts

EP9307

ARM9 SOC with Ethernet, USB, Display and Touchscreen

decrement, or stay at the same value. All DMA

addresses are physical, not virtual addresses.

Reset and Power Management

The chip may be reset through the PRSTn pin or through

the open drain common reset pin, RSTOn.

Clocks are managed on a peripheral-by-peripheral basis

and may be turned off to conserve power.

The processor clock is dynamically adjustable from 0 to

200 MHz (184 MHz for industrial conditions).

Table P. Reset and Power Management Pin Assignments

Pin Mnemonic

Pin Name - Description

PRSTn

RSTOn

Power On Reset

User Reset In/Out – Open Drain –

Preserves Real Time Clock value

Hardware Debug Interface

The JTAG interface allows use of ARM’s Multi-ICE or

other in-circuit emulators.

Table Q. Hardware Debug Interface

Pin Mnemonic

Pin Name - Description

TCK

TDI

TDO

TMS

TRSTn

JTAG Clock

JTAG Data In

JTAG Data Out

JTAG Test Mode Select

JTAG Port Reset

12-Channel DMA Controller

The DMA module contains 12 separate DMA channels.

These may be used for peripheral-to-memory or

memory-to-peripheral access. Two of these are

dedicated to memory-to-memory transfers. Each DMA

channel is connected to the 16-bit DMA request bus.

The request bus is a collection of requests, Serial Audio

and UARTs. Each DMA channel can be used

independently or dedicated to any request signal. For

each DMA channel, source and destination addressing

can be independently programmed to increment,

DS667F2

Copyright 2010 Cirrus Logic (All Rights Reserved)

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