5962F9563501V9A View Datasheet(PDF) - Intersil
Part Name
Description
Manufacturer
5962F9563501V9A Datasheet PDF : 36 Pages
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Timing Diagrams (Continued)
HS-RTX2010RH
PCLK
MA
LDS
UDS
NEW
BOOT
MR/W
MD
IN
MD
OUT
t26
t29
t32
t34
t28
t31
t21
t22
t35
t33
NOTES:
5. If both LDS and UDS are low, no memory access is taking place in the current cycle. This only occurs during streamed instructions that do not
access memory.
6. During a streamed single cycle instruction, the Memory Data Bus is driven by the processor.
FIGURE 4. MEMORY BUS TIMING
ICLK
GIO
PCLK
GA
GR/ W
GD
IN
GD
OUT
t48
t52
t56
t61
t50
t49
t40A, B
t41A, B
t62
t51
t69
t54
t58
t43
t42
t65
t63
NOTES:
7. GIO remains high for internal ASIC bus cycles.
8. GR/W goes low and GD is driven for all ASIC write cycles, including internal ones.
9. During non-ASIC write cycles, GD is not driven by the HS-RTX2010RH. Therefore, it is recommended that all GD pins be pulled to VCC or GND
to minimize power supply current and noise.
10. t40B and t41B specifications are for Streamed Mode of operation only.
FIGURE 5. ASIC BUS TIMING
7
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