HS-RTX2010RH
The Leading Zero Detector is used to normalize the double
word operand contained in the TOP and EXT registers.
The number of leading zeroes in the double word operand
are counted, and the count stored in the MXR register. The
double word operand is then logically shifted left by this
count, and the result stored in the MHR and MLR
registers. Again the upper 16 bits are in MHR , and the
lower 16 bits are in MLR . This entire operation is done in
one clock cycle with the normalize instruction.
HS-RTX2010RH ASIC Bus Interface
The HS-RTX2010RH ASIC Bus services both internal
processor core registers and the on-chip peripheral
registers, and eight external off-chip ASIC Bus locations. All
ASIC Bus operations require a single cycle to execute and
transfer a full 16-bit word of data. The external ASIC Bus
maps into the last eight locations of the 32 location ASIC
Address Space. The three least significant bits of the
address are available as the ASIC Address Bus. The
addresses therefore map as shown in Table 5.
TABLE 5. ASIC BUS MAP
ASIC BUS SIGNAL
GA02
GA01
GA00
ASIC ADDRESS
0
0
0
18H
0
0
1
19H
0
1
0
1AH
0
1
1
1BH
1
0
0
1CH
1
0
1
1DH
1
1
0
1EH
1
1
1
1FH
HS-RTX2010RH Extended Cycle Operation
The HS-RTX2010RH bus cycle operation can be optionally
extended for two types of accesses:
1. USER Memory Cycles
2. ASIC Bus Read Operations
The extension of normal HS-RTX2010RH bus cycle timing
allows the interface of the processor to some peripherals,
and slow memory devices, without using externally
generated wait states. The bus cycle is extended by the
same amount (1 TCLK) as it would be if one wait state was
added to the cycle, but the control signal timing is somewhat
different (see Timing Diagrams). In a one wait state bus
cycle, PCLK is High for 1/2 TCLK period, and Low for 1-1/2
TCLK periods (i.e., PCLK is held Low for one additional
TCLK period). In an extended cycle, PCLK is High for 1
TCLK period, and Low for 1 TCLK period (i.e., both the High
and Low portions of the PCLK period are extended by 1/2
TCLK period).
Setting the Cycle Extend bit (CYCEXT), which is bit 7 of the
IBC Register, will cause extended cycles to be used for all
accesses to USER memory. Setting the ASIC Read Cycle
Extend bit (ARCE), which is bit 13 of the CR Register, will
cause extended cycles to be used for all Read accesses on
the external ASIC Bus. Both the CYCEXT bit and the ARCE
bit are cleared on Reset.
HS-RTX2010RH Memory Access
The HS-RTX2010RH Memory Bus Interface
The HS-RTX2010RH can address 1 Megabyte of memory,
divided into 16 non-overlapping pages of 64K bytes. The
memory page accessed depends on whether the memory
access is for Code (instructions and literals), Data, User
Memory, or Interrupt Code. The page selected also depends
on the contents of the Page Control Registers: the Code
Page Register ( CPR ), the Data Page Register ( DPR ), the
User Page Register ( UPR ), and the Index Page Register
( IPR ). Furthermore, the User Base Address Register
( UBR ) and the Interrupt Base/Control Register ( IBC ) are
used to determine the complete address for User Memory
accesses and Interrupt Acknowledge cycles. External
memory data is accessed through EXT.
When executing code other than an Interrupt Service
routine, the memory page is determined by the contents of
the CPR . Bits 03-00 generate address bits MA19-MA16, as
shown in Figure 18. The remainder of the address (MA15-
MA01) comes from the Program Counter Register ( PC ).
After resetting the processor, both the PC and the CPR
are cleared and execution begins at page 0, word 0.
A new Code page is selected by writing a 4-bit value to the
CPR . The value for the Code page is input to the CPR
through a preload procedure which withholds the value for
one clock cycle before loading the CPR to ensure that the
next instruction is executed from the same Code page as the
instruction which set the new Code page. Execution
immediately thereafter will continue with the next instruction
in the new page.
An Interrupt Acknowledge cycle is a special case of an
Instruction Fetch cycle. When an Interrupt Acknowledge
cycle occurs, the contents of the CPR and PC are saved
on the Return Stack and then the CPR is cleared to point to
page 0. The Interrupt Controller generates a 16-bit address,
or “vector”, which points to the code to be executed to
process the interrupt. To determine how the Interrupt Vector
is formed, refer to Figure 12 for the register bit assignments,
and also to the Interrupt Controller section.
The page for data access is provided by either CPR or
DPR , as shown in Figures 18 and 20. Data Memory
Access instructions can be used to access data in a memory
page other than that containing the program code. This is
done by writing the desired page number into the Data Page
Register ( DPR ) and setting bit 5 (DPRSEL) of the IBC
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