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TAS5706A View Datasheet(PDF) - Texas Instruments

Part NameTAS5706A TI
Texas Instruments TI
Description20-W Stereo Digital Audio Power Amplifier with EQ and DRC
TAS5706A Datasheet PDF : 71 Pages
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TAS5706A
TAS5706B
TAS5706A is Not Recommended for New Designs
SLOS606D – MARCH 2009 – REVISED SEPTEMBER 2009............................................................................................................................................. www.ti.com
PIN FUNCTIONS (continued)
PIN
TYPE
5-V
TERMINATION
NAME
NO.
(1)
TOLERANT
(2)
DESCRIPTION
RESET
SCL
16
DI
5-V
29
DI
5-V
Pullup
Reset, active-low. A system reset is generated by applying a logic low
to this terminal. RESET is an asynchronous control signal that
restores the DAP to its default conditions, sets the VALID outputs low,
and places the PWM in the hard-mute state (stops switching). Master
volume is immediately set to full attenuation. Upon the release of
RESET, if PDN is high, the system performs a 4- to 5-ms device
initialization and sets the volume at mute.
I2C serial control clock input
SCLK
SDA
23
DI
5-V
28
DIO
5-V
Serial audio data clock (shift clock). SCLK is the serial audio port input
data bit clock.
I2C serial control data interface input/output
SDIN1
25
DI
5-V
Serial audio data-1 input is one of the serial data input ports. SDIN1
supports three discrete (stereo) data formats.
SDIN2
24
DI
5-V
Serial audio data-2 input is one of the serial data input ports. SDIN2
supports three discrete (stereo) data formats.
STEST
31
DI
Test terminal. Connect directly to GND.
SUB_PWM–
39
DO
Subwoofer negative PWM output
SUB_PWM+ 40
DO
Subwoofer positive PWM output
TEST2
32
DI
Test terminal. Connect directly to DVDD.
VALID
36
DO
Output indicating validity of ALL PWM channels, active-high. This
terminal is connected to an external power stage. If no external power
stage is used, leave this terminal floating.
VCLAMP_AB 60
P
Internally generated voltage supply for channels A and B gate drive.
Not to be used as a supply or connected to any component other than
the decoupling capacitor
VCLAMP_CD 54
P
Internally generated voltage supply for channels C and D gate drive.
Not to be used as a supply or connected to any component other than
the decoupling capacitor
VR_ANA
14
P
Internally regulated 1.8-V analog supply voltage. This terminal must
not be used to power external devices.
VR_DIG
27
P
Internally regulated 1.8-V digital supply voltage. This terminal must not
be used to power external devices.
VREG_EN
18
DI
Pulldown
Voltage regulator enable. Connect directly to GND.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted) (1)
Supply voltage
DVDD, AVDD
PVCC
Input voltage
3.3-V digital input
5-V tolerant(2) digital input
Input clamp current, IIK (VI < 0 or VI > 1.8 V
Output clamp current, IOK (VO < 0 or VO > 1.8 V
Operating free-air temperature
Operating junction temperature range
Storage temperature range, Tstg
VALUE
–0.3 to 3.6
-0.3 to 30
–0.5 to DVDD + 0.5
–0.5 to DVDD + 2.5
±20
±20
0 to 85
0 to 150
–40 to 125
UNIT
V
V
V
V
mA
mA
°C
°C
°C
(1) Stresses beyond those listed under absolute ratings may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under recommended operation conditions are
not implied. Exposure to absolute-maximum conditions for extended periods may affect device reliability.
(2) 5-V tolerant inputs are PDN, RESET, MUTE, SCLK, LRCLK, MCLK, SDIN1, SDIN2, SDA, SCL, and HPSEL.
8
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