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TAS5706A View Datasheet(PDF) - Texas Instruments

Part NameTAS5706A TI
Texas Instruments TI
Description20-W Stereo Digital Audio Power Amplifier with EQ and DRC


TAS5706A Datasheet PDF : 71 Pages
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TAS5706A is Not Recommended for New Designs
TAS5706A
TAS5706B
www.ti.com............................................................................................................................................. SLOS606D – MARCH 2009 – REVISED SEPTEMBER 2009
PIN
NAME
BST_A
BST_B
BST_C
BST_D
BYPASS
DVDD
DVSS
HPL_PWM
HPR_PWM
HPSEL
LRCLK
MCLK
MUTE
OSC_RES
OUT_A
OUT_B
OUT_C
OUT_D
PDN
PGND_A
PGND_B
PGND_C
PGND_D
PLL_FLTM
PLL_FLTP
PVCC_A
PVCC_B
PVCC_C
PVCC_D
NO.
59
61
53
55
56
15,
33
20,
26
37
38
30
22
34
21
19
4, 5
1, 64
49,
50
45,
46
17
6, 7
2, 3
47,
48
43,
44
12
13
8, 9
62,
63
51,
52
41,
42
TYPE
(1)
P
P
P
P
O
P
P
DO
DO
DI
DI
DI
DI
AO
O
O
O
O
DI
P
P
P
P
AO
AI
P
P
P
P
PIN FUNCTIONS (continued)
5-V
TERMINATION
TOLERANT
(2)
DESCRIPTION
High-side bootstrap supply for half-bridge A
High-side bootstrap supply for half-bridge B
High-side bootstrap supply for half-bridge C
High-side bootstrap supply for half-bridge D
Nominally equal to VCC/8. Internal reference voltage for analog cells
3.3-V digital power supply
Digital ground
Headphone left-channel PWM output.
Headphone right-channel PWM output.
Headphone select, active high. When a logic HIGH is applied, device
5-V
enters headphone mode and speakers are HARD MUTED. When a
logic LOW is applied, device is in speaker mode and headphone
outputs become line outputs or are disabled.
5-V
Input serial audio data left/right clock (sampling rate clock)
5-V
MCLK is the clock master input. The input frequency of this clock can
range from 4.9 MHz to 49 MHz.
Performs a soft mute of outputs, active-low. A logic low on this
terminal sets the outputs equal to 50% duty cycle. A logic high on this
5-V
Pullup
terminal allows normal operation. The mute control provides a
noiseless volume ramp to silence. Releasing mute provides a
noiseless ramp to previous volume.
Oscillator trim resistor. Connect an 18.2-kresistor to GND.
Output, half-bridge A
Output, half-bridge B
Output, half-bridge C
Output, half-bridge D
Power down, active-low. PDN powers down all logic, stops all clocks,
5-V
Pullup
and outputs stops switching. When PDN is released, the device
powers up all logic, starts all clocks, and performs a soft start that
returns to the previous configuration determined by register settings.
Power ground for half-bridge A
Power ground for half-bridge B
Power ground for half-bridge C
Power ground for half-bridge D
PLL negative input
PLL positive input
Power supply input for half-bridge output A
Power supply input for half-bridge output B
Power supply input for half-bridge output C
Power supply input for half-bridge output D
Copyright © 2009, Texas Instruments Incorporated
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