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TAS5706A View Datasheet(PDF) - Texas Instruments

Part NameTAS5706A TI
Texas Instruments TI
Description20-W Stereo Digital Audio Power Amplifier with EQ and DRC
TAS5706A Datasheet PDF : 71 Pages
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TAS5706A is Not Recommended for New Designs
TAS5706A
TAS5706B
www.ti.com............................................................................................................................................. SLOS606D – MARCH 2009 – REVISED SEPTEMBER 2009
MODULATION LIMIT REGISTER (0x10)
Set modulation limit. See the appropriate power stage data sheet for recommended modulation limits.
Table 12. Modulation Limit Register (0x10)
D7 D6 D5 D4 D3 D2 D1 D0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
LIMIT
[DCLKs]
1
2
3
4
5
6
7
8
MIN WIDTH [DCLKs] MODULATION LIMIT
2
99.2%
4
98.4%
6
97.7%
8
96.9%
10
96.1%
12
95.3%
14
94.5%
16
93.8%
INTERCHANNEL DELAY REGISTERS (0x11, 0x12, 0x13, 0x14, 0x15, 0x16)
Internal PWM Channels 1, 2, 3, 4, 5, and 6 are mapped into registers 0x11, 0x12 ,0x13, 0x14, 0x15, and 0x16.
Table 13. Channel Interchannel Delay Register Format
BITS DEFINITION D7 D6 D5 D4 D3 D2 D1 D0
FUNCTION
0
0
0
0
0
0
0
0
Minimum absolute delay, 0 DCLK cycles, default for
channel 0 (1)
0
1
1
1
1
1
0
0 Maximum positive delay, 31 × 4 DCLK cycles
1
0
0
0
0
0
0
0 Maximum negative delay, –32 × 4 DCLK cycles
0
0 Unused bits
SUBADDRESS
0x11
0x12
0x13
0x14
0x15
0x16
A
D7 D6 D5 D4 D3 D2 D1 D0 Delay = (value) × 4 DCLKs
0
1
0
0
1
1
0
0 Default value for channel 1 (1) 19
0
0
1
1
0
1
0
0 Default value for channel 2 (1) 13
0
0
0
1
1
1
0
0 Default value for channel 3 (1) 7
0
1
1
0
0
1
0
0 Default value for channel 4 (1) 25
1
1
0
1
0
0
0
0 Default value for channel 5 (1) –12
1
0
0
1
0
0
0
0 Default value for channel 6 (1) -28
(1) Default values are in bold.
OFFSET REGISTER (0x17)
The offset register is mapped into 0x17.
D7 D6 D5 D4 D3 D2
00000 0
11111 1
(1) Default values are in bold.
Table 14. Channel Offset Register Format
D1 D0
FUNCTION
0
0 Minimum absolute offset, 0 DCLK cycles, default for channel 0 (1)
1
1 Maximum absolute offset, 255 DCLK cycles
Copyright © 2009, Texas Instruments Incorporated
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