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TAS5706A View Datasheet(PDF) - Texas Instruments

Part NameTAS5706A TI
Texas Instruments TI
Description20-W Stereo Digital Audio Power Amplifier with EQ and DRC


TAS5706A Datasheet PDF : 71 Pages
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TAS5706A
TAS5706B
TAS5706A is Not Recommended for New Designs
SLOS606D – MARCH 2009 – REVISED SEPTEMBER 2009............................................................................................................................................. www.ti.com
Right-Justified
Right-justified (RJ) timing uses LRCLK to define when the data being transmitted is for the left channel and when
it is for the right channel. LRCLK is high for the left channel and low for the right channel. A bit clock running at
32, 48, or 64 × fS is used to clock in the data. The first bit of data appears on the data 8 bit-clock periods (for
24-bit data) after LRCLK toggles. In RJ mode the LSB of data is always clocked by the last bit clock before
LRCLK transitions. The data is written MSB first and is valid on the rising edge of bit clock. The DAP masks
unused leading data bit positions.
2-Channel Right-Justified (Sony Format) Stereo Input
LRCLK
32 Clks
Left Channel
32 Clks
Right Channel
SCLK
SCLK
MSB
24-Bit Mode
20-Bit Mode
16-Bit Mode
23 22
19 18
19 18
15 14
15 14
15 14
LSB MSB
10
10
10
23 22
19 18
15 14
19 18
15 14
15 14
Figure 36. Right Justified 64-fS Format
LSB
10
10
10
T0034-03
28
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