RTD2120 View Datasheet(PDF) - Realtek Semiconductor

Part Name

Description

Manufacturer

RTD2120

8051 Embedded Micro-Controller for Monitor

Realtek Semiconductor 

Realtek

RTD2120-series

DW8051 micro-processor

The DW8051 contained in RTD2120 is compatible with industry standard 803x/805x and

provides the following design features and enhancements to the standard 8051 microcontroller:

1. High speed architecture

Compared to standard 8051, the DW8051 processor core provides increased performance by

executing instructions in a 4-clock bus cycle, as opposed to the 12-clock bus cycle in the standard

8051. The shortened bus timing improves the instruction execution rate for most instructions by a

factor of three over the standard 8051 architectures. The average speed improvement for the entire

instruction set is approximately 2.5X.

2. Stretch Memory Cycles

The stretch memory cycle feature enables application software to adjust the speed of data

memory access. The DW8051 can execute the MOVX instruction in as little as 2 instruction cycles.

However, it is sometimes desirable to stretch this value; for example, to access slow memory or slow

memory-mapped peripherals such as UARTs or LCDs.

The three LSBs of the Clock Control Register (at SFR location 8Eh) control the stretch value.

You can use stretch values between zero and seven. A stretch value of zero adds zero instruction

cycles, resulting in MOVX instructions executing in two instruction cycles. A stretch value of seven

adds seven instruction cycles, resulting in MOVX instructions executing in nine instruction cycles.

The stretch value can be changed dynamically under program control.

By default, the stretch value resets to one (three cycle MOVX). For full-speed data memory

access, the software must set the stretch value to zero. The stretch value affects only data memory

access. The only way to reduce the speed of program memory (ROM) access is to use a slower clock.

3. Dual Data Pointers

The DW8051 employs dual data pointers to accelerate data memory block moves. The standard

8051 data pointer (DPTR) is a 16-bit value used to address external data RAM or peripherals. The

DW8051 maintains the standard data pointer as DPTR0 at SFR locations 82h and 83h. It is not

necessary to modify code to use DPTR0.

The DW8051 adds a second data pointer (DPTR1) at SFR locations 84h and 85h. The SEL bit in

the DPTR Select register, DPS (SFR 86h), selects the active pointer. When SEL = 0, instructions that

use the DPTR will use DPL0 and DPH0. When SEL = 1, instructions that use the DPTR will use

DPL1 and DPH1. SEL is the bit 0 of SFR location 86h. No other bits of SFR location 86h are used.

All DPTR-related instructions use the currently selected data pointer. To switch the active

pointer, toggle the SEL bit. The fastest way to do so is to use the increment instruction (INC DPS).

This requires only one instruction to switch from a source address to a destination address, saving

application code from having to save source and destination addresses when doing a block move.

Using dual data pointers provides significantly increased efficiency when moving large blocks of

data.

4. Timer Rate Control

One important difference exists between the RTD2120 and 80C32 regarding timers. The original

80C32 used a 12 clock per cycle scheme for timers and consequently for some serial baud

rates(depending on the mode). The RTD2120 architecture normally runs using 4 clocks per cycle.

However, in the area of timers, it will default to a 12 clock per cycle scheme on a reset. This allows

existing code with real–time dependencies such as baud rates to operate properly. If an application

needs higher speed timers or serial baud rates, the timers can be set to run at the 4 clock rate.

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