RTD2120 View Datasheet(PDF) - Realtek Semiconductor
Part Name
Description
Manufacturer
RTD2120 Datasheet PDF : 37 Pages
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Realtek
RTD2120-series
1: bypass
reserved
3
--
0
Reserved
CNT1
2:0
R/W
0
The number N of counter1
000~111: 1~8
l When ISP mode is enabled, watchdog will be disabled by hardware.
*When BY_CNT2 and BY_CNT3 are all assigned one (bypass), watchdog will be counted by CNT2
In System Programming
User can program the embedded 96K flash of RTD2120 by internal hardware without removing
RTD2120 from the system. RTD2120 utilizes DDC channel (ADC/DVI DDC) to communicate with
IIC host for ISP function. The ISP protocol is mainly compatible with DDC protocol. However, one
significant difference is that the LSB of 7-bit ISP address is the address auto increase bit. Thus, we can
improve the flash program speed.
Register::ISP_slave_address
0xFF37
Name
Bits
Read/Write Reset State Comments
ISP_ADDR
7:2
R/W
ISP_ADDR_I
1
R
NC_A
ISP_ADDR_I
0
R
NC_D
25
ISP slave address
1
Received LSB of ISP slave address of ADC
DDC channel
0: address is nonincrease
1: address is auto-increase
1
Received LSB of ISP slave address of DVI
DDC channel
0: address is nonincrease
1: address is auto-increase
Register::option
0xFF38
Name
Bits
Read/Write Reset State Comments
PORT_PIN_R
7
R/W
EG
reserved
6:2
--
MCU_CLK_S
1
R/W
EL
CKOUT_SEL
0
R/W
1
port_pin_reg_n enable
0: port_pin_reg_n signal is disabled
1: port_pin_reg_n signal is enabled
0
Reserved
0
CPU clock source select
0: CPU clock is from Crystal divided by DIV
1: CPU clock is from PLL divided by DIV
0
CLKO1 & CLKO2 select
0: Select Crystal output
1: Select PLL output
Register::flash_page_erase_control
Name
Bits
Read/Write Reset State Comments
0xFF39
confidential
30
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