Realtek
A_DBN_EN
1
R/W
A_DDC_EN
0
R/W
RTD2120-series
0: Disable
1: Enable
1
ADC DDC De-bounce Enable
0: Disable
1: Enable (with crystal/4)
0
ADC DDC Channel Enable Bit
0: MCU access Enable
1: DDC channel Enable
Register::ADC_DDC_control
0xFF21
Name
Bits
Read/Write Reset State Comments
A_DBN_CLK
7:6
R/W
_SEL
A_STOP_DB
5:4
R/W
N_SEL
A_SYS_CK_S
3
R/W
EL
A_DDC2
2
R/W
RST_A_DDC
1
R/W
RVT_A_DDC
0
R/W
1_EN
0
De-bounce clock divider
00: 1/1 reference clock
01: 1/2 reference clock
1X: 1/4 reference clock
0
De-bounce sda stage
0X: latch one stage
10: latch two stage
11: latch three stage
0
De-bounce reference clock
0: crystal clock
1: PLL clock
0
Force to ADC DDC to DDC2 mode
0: Normal operation
1: DDC2 is active
0
Reset ADC DDC circuit
0: Normal operation
1: reset (auto cleared)
0
ADC DDC revert to DDC1 enable(SCL idle
for 128 VSYNC)
0: Disable
1: Enable
Register::DVI_DDC_enable
0xFF23
Name
Bits
Read/Write Reset State Comments
D_DDC_ADD 7:5
R/W
R
reserved
4
--
D_DDC_W_S
3
R/W
TA
D_DDCRAM
2
R/W
_W_EN
D_DBN_EN
1
R/W
0
DVI DDC Channel Address Least
Significant 3 Bits
(The default DDC channel address MSB 4
Bits is “A”)
0
Reserved
0
DVI DDC External Write Status (for external
DDC access only)
It is cleared after write.
0
DVI DDC External Write Enable (for
external DDC access only)
0: Disable
1: Enable
1
DVI DDC Debounce Enable
0: Disable
1: Enable (with crystal/4)
confidential
24