AD6657
ANALOG XFMR 1:4 Z
INPUT ETC4-1T-7
0.1µF
0.1µF
121Ω
INPUT
Z = 50Ω
0.1µF
0.1µF 121Ω
0.1µF
33Ω
431nH
3.0kΩ
33Ω AIN–
VCM
3.0pF
ADC
INTERNAL
INPUT Z
Figure 34. 1:4 Transformer Passive Configuration
1000pF 180nH 220nH
1µH
AD8376
1µH
VPOS
165Ω
301Ω 5.1pF 3.9pF
1nF
165Ω
15pF
VCM
1nF
3.0kΩ║3.0pF
68nH AD6657
1000pF 180nH 220nH
NOTES
1. ALL INDUCTORS ARE COILCRAFT 0603CS COMPONENTS
WITH THE EXCEPTION OF THE 1µH CHOKE INDUCTORS (0603LS).
Figure 35. Active Front-End Configuration Using the AD8376
Data Sheet
For the popular IF band of 140 MHz, Figure 34 shows an
example of a 1:4 transformer passive configuration where a
differential inductor is used to resonate with the internal input
capacitance of the AD6657. This configuration realizes excellent
noise and distortion performance. Figure 35 shows an example
of an active front-end configuration using the AD8376 dual
VGA. This configuration is recommended when signal gain
is required.
CLOCK INPUT CONSIDERATIONS
For optimum performance, the AD6657 sample clock inputs,
CLK+ and CLK−, should be clocked with a differential signal.
The signal is typically ac-coupled into the CLK+ and CLK− pins
via a transformer or capacitors. These pins are biased internally
(see Figure 36) and require no external bias.
AVDD
CLK+
2pF
1.2V
CLK–
2pF
Figure 36. Equivalent Clock Input Circuit
Clock Input Options
The AD6657 has a very flexible clock input structure. The clock
input can be a CMOS, LVDS, LVPECL, or sine wave signal.
Regardless of the type of signal being used, clock source jitter is
of the most concern (see the Jitter Considerations section).
Figure 37 and Figure 38 show two preferred methods for clock-
ing the AD6657 (at clock rates up to 625 MHz). A low jitter clock
source is converted from a single-ended signal to a differential
signal using either an RF balun or an RF transformer.
The RF balun configuration is recommended for clock frequencies
between 125 MHz and 625 MHz, and the RF transformer config-
uration is recommended for clock frequencies from 10 MHz to
200 MHz. The back-to-back Schottky diodes across the trans-
former/balun secondary limit clock excursions into the AD6657
to approximately 0.8 V p-p differential.
This limit helps to prevent the large voltage swings of the clock
from feeding through to other portions of the AD6657 while
preserving the fast rise and fall times of the signal that are
critical to a low jitter performance.
CLOCK
INPUT
0.1µF
ADT1-1WT, 1:1Z
XFMR 0.1µF
50Ω 100Ω
0.1µF
0.1µF
SCHOTTKY
DIODES:
HSMS2822
CLK+
ADC
CLK–
Figure 37. Transformer-Coupled Differential Clock (Up to 200 MHz)
CLOCK
INPUT
1nF
50Ω
1nF
0.1µF
0.1µF
SCHOTTKY
DIODES:
HSMS2822
CLK+
ADC
CLK–
Figure 38. Balun-Coupled Differential Clock (Up to 625 MHz)
Rev. B | Page 18 of 32