AD6657
MEMORY MAP REGISTER TABLE
All address and bit locations that are not included in Table 13 are not currently supported for this device.
Table 13. Memory Map Registers
Addr. Register
(Hex) Name
(MSB)
Bit 7
Chip Configuration Registers
0x00 SPI port
Open
configuration
(global)
Bit 6
LSB first
0x01 Chip ID
(global)
Channel Index and Transfer Registers
0x05 Channel
index
Enable
output
port for
Channel C
and
Channel D
Enable
output
port for
Channel
A and
Channel
B
0xFF Transfer
Open
Open
ADC Function Registers
0x08 Power modes Open
Open
0x0B Clock divide
(global)
Open
Open
0x0C Shuffle mode Open
(local)
Open
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
(LSB)
Bit 0
Default
Value
(Hex) Comments
Soft reset 1
1
Soft reset LSB first Open
8-bit chip ID, Bits[7:0]
AD6657 = 0x0C (default)
0x18
0x0C
Nibbles are
mirrored so
that LSB first
or MSB first
mode is set
correctly,
regardless of
shift mode.
To control
this register,
all channel
index bits in
Register 0x05
must be set.
Read only.
Open
Open
Open
Open
Channel Channel
D enable C enable
Channel Channel 0xCF
B enable A enable
Open Open
Open
SW
transfer
1 = on
0 = off
(default)
0x00
Bits are set to
determine
which
channel
on the chip
receives the
next write
command;
applies to
local registers.
Synchro-
nously
transfers
data from
the master
shift register
to the slave.
External
power-
down pin
function
(global)
0 = full
power-
down
1=
standby
Open
Open
Clock divide phase
000 = 0 input clock cycles delayed
001 = 1 input clock cycle delayed
010 = 2 input clock cycles delayed
Open
Open
Open
Open
Internal power-down
mode (local)
00 = normal operation
(default)
01 = full power-down
10 = standby
Clock divide ratio
000 = divide by 1
001 = divide by 2
010 = divide by 3
011 = divide by 4
100 = divide by 5
101 = divide by 6
110 = divide by 7
111 = divide by 8
Open
Shuffle mode enable
00 = shuffle disabled
01 = shuffle enabled
0x00
0x00
0x01
Determines
generic
modes
of chip
operation.
Enables or
disables
shuffle mode
Rev. 0 | Page 27 of 32