AD7397AN View Datasheet(PDF) - Analog Devices
Part Name
Description
Manufacturer
AD7397AN Datasheet PDF : 12 Pages
| |||
AD7396/AD7397
1400
1200
1000
800
AD7396
A: VDD = +2.7V, CODE = 555H
B: VDD = +2.7V, CODE = 3FFH
C: VDD = +5.5V, CODE = 155H
D: VDD = +5.5V, CODE = 3FFH
600
D
C
400
200
A
B
0
1k
10k
100k
1M
10M
DIGITAL INPUT FREQUENCY – Hz
Figure 22. IDD vs. Digital Input
Frequency
80
70
VDD = +5V, ؎5%
60
50
40 VDD = +3V, ؎5%
30
20
10
0
1
10
100
1k
10k
FREQUENCY – Hz
Figure 23. PSRR vs. Frequency
1.0
AD7396
0.9
SAMPLE SIZE = 77
0.8 VREF = +2.5V
0.7
0.6
0.5
CODE = FFFH
0.4
0.3
0.2
CODE = 000H
0.1
0
0 100 200 300 400 500 600
HOURS OF OPERATION AT +150؇C
Figure 24. Long-Term Drift Acceler-
ated by Burn-In
OPERATION
The AD7396 and AD7397 are a set of pin compatible, 12-bit
and 10-bit digital-to-analog converters. These single-supply
operation devices consume less than 200 µA of current while
operating from power supplies in the +2.7 V to +5.5 V range,
making them ideal for battery operated applications. They
contain a voltage-switched, 12-bit/10-bit, digital-to-analog
converter, rail-to-rail output op amps, and a parallel-input
DAC register. The external reference input has constant
2.5 MΩ input resistance independent of the digital code
setting of the DAC. In addition, the reference input can be tied
to the same supply voltage as VDD resulting in a maximum
output voltage span of 0 to VDD. The parallel data interface
consists of 12 data bits, DB0–DB11, for the AD7396, 10 data
bits, DB0–DB9, for the AD7397, and a CS write strobe. An RS
pin is available to reset the DAC register to zero scale. This
function is useful for power-on reset or system failure recovery
to a known state. Additional power savings are accomplished by
activating the SHDN pin resulting in a 1.5 µA maximum con-
sumption sleep mode. As long as the supply voltage, remains
data will be retained in the DAC and input register to supply
the DAC output when the part is taken out of shutdown.
AD7396
LDA
DACA
REGISTER
12
12-BIT
DACA
VDD
VOUTA
CS
A/B
DATA
INPUTA
REGISTER
12
1
INPUTB
REGISTER
VREF
LDB
DACB
REGISTER
12
12-BIT
DACB
VOUTB
AGND
DGND
RS
SHDN
Figure 25. Functional Block Diagram
D/A CONVERTER SECTION
The voltage switched R-2R DAC generates an output voltage
dependent on the external reference voltage connected to the
REF pin according to the following equation:
VOUT = VREF × D/2N
(1)
where D is the decimal data word loaded into the DAC register,
and N is the number of bits of DAC resolution. In the case of
the 10-bit AD7397 using a 2.5 V reference, Equation 1 simpli-
fies to:
VOUT = 2.5 × D/1024
(2)
Using Equation 2, the nominal midscale voltage at VOUT is
1.25 V for D = 512; full-scale voltage is 2.497 V. The LSB step
size is = 2.5 × 1/1024 = 0.0024 V.
For the 12-bit AD7396 operating from a 5.0 V reference equa-
tion [1] becomes:
VOUT = 5.0 × D/4096
(3)
Using Equation 3, the AD7396 provides a nominal midscale
voltage of 2.50 V for D = 2048, and a full-scale output of
4.998 V. The LSB step size is = 5.0 × 1/4096 = 0.0012 V.
AMPLIFIER SECTION
The internal DAC’s output is buffered by a low power con-
sumption precision amplifier. The op amp has a 60 µs typical
settling time to 0.1% of full scale. There are slight differences in
settling time for negative slewing signals versus positive. Also,
negative transition settling time to within the last 6 LSBs of zero
volts has an extended settling time. The rail-to-rail output stage
of this amplifier has been designed to provide precision perfor-
mance while operating near either power supply. Figure 26
shows an equivalent output schematic of the rail-to-rail-ampli-
fier with its N-channel pull-down FETs that will pull an output
load directly to GND. The output sourcing current is provided
by a P-channel pull-up device that can source current to GND
terminated loads.
VDD
P-ch
N-ch
VOUT
AGND
Figure 26. Equivalent Analog Output Circuit
REV. 0
–9–
|
|
Share Link: 