AD7397AR View Datasheet(PDF) - Analog Devices
Part Name
Description
Manufacturer
AD7397AR Datasheet PDF : 12 Pages
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AD7396/AD7397
CS
A/B
D0–D11
LDA, LDB
RS
VOUT
tCSW
tAS
tAH
tDS
tDH
tLS
tLH
tS
tLDW
tRSW
tS
1 LSB
ERROR BAND
Figure 2. Timing Diagram
DBx
CS
A/B
RS
B REGISTER
1 OF 12
LATCHES
OF THE 2 INPUT
REGISTERS
TO DAC
REGISTERS
Figure 3. Digital Control Logic
Table I. Control Logic Truth
CS A/B LDA LDB RS SHDN
Input Register
DAC Register
L
L
H
H
H
X
L
H
H
H
H
X
L
L
H
L
H
X
L
H
L
H
H
X
H
X
L
L
H
X
H
X
^
^
H
X
X
X
X
X
L
X
H
X
X
X
^
X
Write to B
Write to A
Write to B
Write to A
Latched
Latched
Reset to Zero Scale
Latched to Zero
Latched with Previous Data
Latched with Previous Data
B Transparent
A Transparent
A and B Transparent
Latched with New Data from Input REG
Reset to Zero Scale
Latched to Zero
^Denotes positive edge. The SHDN pin has no effect on the digital interface data loading; however, while in the SHDN state (SHDN = 0) the output amplifiers VOUTA
and VOUTB exhibit an open circuit condition. Note, the LDx inputs are level-sensitive, the respective DAC registers are in a transparent state when LDx = “0.”
–4–
REV. 0
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