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DAC8043AFRUZ3 View Datasheet(PDF) - Analog Devices

Part Name
Description
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DAC8043AFRUZ3 Datasheet PDF : 9 Pages
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DAC8043A
PARAMETER DEFINITIONS
INTEGRAL NONLINEARITY (INL)
This is the single most important DAC specification. ADI mea-
sures INL as the maximum deviation of the analog output (from
the ideal) from a straight line drawn between the end points. It
is expressed as a percent of full-scale range or in terms of LSBs.
Refer to Analog Devices Data Reference Manual for additional
digital-to-analog converter definitions.
INTERFACE LOGIC INFORMATION
The DAC8043A has been designed for ease of operation. The
timing diagram, Figure 2, illustrates the input register loading
sequence. Note that the most significant bit (MSB) is loaded
first. Once the 12-bit input register is full, the data is transferred
to the DAC register by taking LD momentarily low.
DIGITAL SECTION
The DAC8043A’s digital inputs, SRI, LD, and CLK, are TTL
compatible. The input voltage levels affect the amount of cur-
rent drawn from the supply; peak supply current occurs as the
digital input (VIN) passes through the transition region. See the
Supply Current vs. Logic Input Voltage graph located in the
typical performance characteristics curves. Maintaining the
digital input voltage levels as close as possible to the supplies,
VDD and GND, minimizes supply current consumption. The
DAC8043A’s digital inputs have been designed with ESD resis-
tance incorporated through careful layout and the inclusion of
input protection circuitry. Figure 17 shows the input protection
diodes and series resistor; this input structure is duplicated on
each digital input. High voltage static charges applied to the
inputs are shunted to the supply and ground rails through for-
ward biased diodes. These protection diodes were designed to
clamp the inputs to well below dangerous levels during static
discharge conditions.
VDD
LD, CLK, SRI
5k
GND
Figure 17. Digital Input Protection
GENERAL CIRCUIT INFORMATION
The DAC8043A is a 12-bit multiplying D/A converter with a
very low temperature coefficient. It contains an R-2R resistor
ladder network, data input and control logic, and two data
registers.
The digital circuitry forms an interface in which serial data can
be loaded under microprocessor control into a 12-bit shift regis-
ter and then transferred, in parallel, to the 12-bit DAC register.
The analog portion of the DAC8043A contains an inverted
R-2R ladder network consisting of silicon-chrome, highly-stable
(50 ppm/°C) thin-film resistors, and twelve pairs of NMOS
current-steering switches, see Figure 18. These switches steer
binarily weighted currents into either IOUT or GND; this yields a
constant current in each ladder leg, regardless of digital input
code. This constant current results in a constant input resis-
tance at VREF equal to R. The VREF input may be driven by any
reference voltage or current, ac or dc that is within the limits
stated in the Absolute Maximum Ratings.
VREF
10k
10k
10k
20k
S1
20k
S2
20k
S3
20k
S12
20k
*
BIT 1 (MSB) BIT 2
BIT 3 BIT 12 (LSB)
DIGITAL INPUTS
(SWITCHES SHOWN FOR DIGITAL INPUTS "HIGH")
*THESE SWITCHES PERMANENTLY "ON"
10k
*
GND
IOUT
RFEEDBACK
Figure 18. Simplified DAC Circuit
The twelve output current steering NMOS FET switches are in
series with each R-2R resistor.
To further ensure accuracy across the full temperature range,
permanently “ON” MOS switches were included in series with
the feedback resistor and the R-2R ladder’s terminating resistor.
Figure 18 shows the location of the series switches. During any
testing of the resistor ladder or RFEEDBACK (such as incoming
inspection), VDD must be present to turn “ON” these series
switches.
DYNAMIC PERFORMANCE
OUTPUT IMPEDANCE
The DAC8043A’s output resistance, as in the case of the output
capacitance, varies with the digital input code. This resistance,
looking back into the IOUT terminal, may be between 10 k(the
feedback resistor alone when all digital inputs are LOW) and
7.5 k(the feedback resistor in parallel with approximate 30 k
of the R-2R ladder network resistance when any single bit logic
is HIGH). Static accuracy and dynamic performance will be
affected by these variations.
APPLICATIONS INFORMATION
In most applications, linearity depends upon the potential of the
IOUT and GND pins being at the same voltage potential. The
DAC is connected to an external precision op amp inverting
input. The external amplifiers noninverting input should be tied
directly to ground without the usual bias current compensating
resistor. (See Figures 19 and 20.) The selected amplifier should
have a low input bias current and low drift over temperature.
The amplifiers input offset voltage should be nulled to less than
200 microvolts (less than 10% of 1 LSB). All grounded pins
should tie to a single common ground point to avoid ground loops.
The VDD power supply should have a low noise level with
adequate bypassing. It is best to operate the DAC8043A from
the analog power supply and grounds.
UNIPOLAR 2-QUADRANT MULTIPLYING
The most straightforward application of the DAC8043A is in
the 2-quadrant multiplying configuration shown in Figure 19. If
the reference input signal is replaced with a fixed dc voltage
REV. B
–7–
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