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DAC8043AFRUZ3 View Datasheet(PDF) - Analog Devices

Part Name
Description
Manufacturer
DAC8043AFRUZ3 Datasheet PDF : 9 Pages
1 2 3 4 5 6 7 8 9
DAC8043A–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS (@ VDD = 5 V, VREF = 10 V, –40؇C < TA < +85؇C, unless otherwise noted.)
Parameter
Symbol Condition
E Grade F Grade Unit
STATIC PERFORMANCE
Resolution
Relative Accuracy
Differential Nonlinearity
Gain Error1
Gain Tempco2
Output Leakage Current
Zero-Scale Error3
N
INL
DNL
GFSE
TCGFS
ILKG
IZSE
12
± 0.5
All Grades Monotonic to 12 Bits
± 0.5
TA = 25°C, Data = FFFH
± 1.0
TA = –40°C, +85°C, Data = FFFH
± 2.0
IOUT Pin Measured
±5
Data = 000H, IOUT Pin Measured
±5
TA = –40°C, +85°C, Data = 000H, IOUT Pin Measured ± 25
Data = 000H
0.03
TA = –40°C, +85°C, Data = 000H
0.15
12
± 1.0
± 1.0
± 2.0
± 2.0
±5
±5
± 25
0.03
0.15
Bits
LSB max
LSB max
LSB max
LSB max
ppm/°C max
nA max
nA max
LSB max
LSB max
REFERENCE INPUT
Input Resistance
Input Capacitance2
RREF
CREF
Absolute Tempco < 50 ppm/°C
7/15
7/15
kmin/max
5
5
pF typ
ANALOG OUTPUT
Output Capacitance2
COUT
Data = 000H
Data = FFFH
25
25
pF typ
30
30
pF typ
DIGITAL INPUTS
Digital Input Low
Digital Input High
Input Leakage Current
Input Capacitance2
VIL
VIH
IIL
VLOGIC = 0 V to 5 V
CIL
VLOGIC = 0 V
0.8
2.4
0.001/± 1
10
0.8
2.4
0.001/± 1
10
V max
V min
µA typ/max
pF max
INTERFACE TIMING2, 4
Data Setup
tDS
Data Hold
tDH
Clock Width High
tCH
Clock Width Low
tCL
Load Pulsewidth
tLD
LSB CLK to LD DAC
tASB
10
10
ns min
5
5
ns min
25
25
ns min
25
25
ns min
25
25
ns min
0
0
ns min
AC CHARACTERISTICS1, 2
Output Current Settling Time tS
To ± 0.01% of Full Scale, Ext Op Amp OP42
1
1
µs max
DAC Glitch
Q
Data = 000H to FFFH to 000H, VREF = 0 V
20
20
nVs max
Feedthrough (VOUT/VREF)
FT
VREF = 20 V p-p, Data = 000H, f = 10 kHz
1
1
mV p-p
Total Harmonic Distortion
Output Noise Density5
THD
en
VREF = 6 V rms, Data = FFFH, f = 1 kHz
10 Hz to 100 kHz Between RFB and IOUT
–85
–85
dB typ
17
17
nV/Hz max
Multiplying Bandwidth
BW
–3 dB, VOUT/VREF, VREF = 100 mV rms, Data = FFFH 2.4
2.4
MHz typ
SUPPLY CHARACTERISTICS
Power Supply Range
Positive Supply Current
Power Dissipation
Power Supply Sensitivity
VDD RANGE
IDD
PDISS
PSS
VLOGIC = 0 V or VDD
VLOGIC = 0 V or VDD
VDD = ± 5%
4.5/5.5
10
50
0.002
4.5/5.5
10
50
0.002
V min/max
µA max
µW max
%/% max
NOTES
1Using internal feedback resistor RFB, see Figure 19 test circuit with VREF = 10 V.
2These parameters are guaranteed by design and not subject to production testing.
3Calculated from worst case RREF: IZSE(LSB) = (RREF × ILKG × 4096)/VREF.
4All input control signals are specified with tR = tF = 2 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
5Calculation from en = 4KTRB where: K = Boltzmann Constant (J/°K), R = Resistance (), T = Resistor Temperature (°K), B = 1 Hz Bandwidth.
Specifications subject to change without notice.
–2–
REV. B
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