AD7718BRU View Datasheet(PDF) - Analog Devices

Part Name

Description

Manufacturer

AD7718BRU

8-/10-Channel, Low Voltage, Low Power, Σ-∆ ADCs

Analog Devices 

AD7708/AD7718

The output code for any analog input voltage on the AD7708

can be represented as follows:

Code = (AIN × GAIN × 216)/(1.024 × VREF)

where

AIN is the analog input voltage,

GAIN is the PGA gain, i.e., 1 on the 2.5 V range and 128 on

the 20 mV range.

When an ADC is configured for bipolar operation, the coding is

offset binary with a negative full-scale voltage resulting in a code

of 000 . . . 000, a zero differential voltage resulting in a code of

100 . . . 000, and a positive full-scale voltage resulting in a code

of 111 . . . 111. The output code from the AD7718 for any

analog input voltage can be represented as follows:

Code = 223 × [(AIN × GAIN/(1.024 × VREF)) + 1]

where

AIN is the analog input voltage,

GAIN is the PGA gain, i.e., 1 on the ± 2.5 V range and 128 on

the ± 20 mV range.

The output code from the AD7708 for any analog input voltage

can be represented as follows:

Code = 215 × [(AIN × GAIN/(1.024 × VREF)) + 1]

where

AIN is the analog input voltage,

GAIN is the PGA gain, i.e., 1 on the ± 2.5 V range and 128 on

the ± 20 mV range.

Oscillator Circuit

The AD7708/AD7718 is intended for use with a 32.768 kHz

watch crystal or ceramic resonator. A PLL internally locks onto

a multiple of this frequency to provide a stable 4.194304 MHz

clock for the ADC. The modulator sample rate is the same as

the oscillator frequency.

The start-up time associated with 32 kHz crystals is typically

300 ms. The OSPD bit in the mode register can be used to

prevent the oscillator from powering down when the AD7708/

AD7718 is placed in power-down mode. This avoids having to

wait 300 ms after exiting power-down to start a conversion at

the expense of raising the power-down current.

Reference Input

The AD7708/AD7718 has a fully differential reference input

capability. When the AD7708/AD7718 is configured in 8-channel

mode (CHCON = 0) the user has the option of selecting one of

two reference options. This allows the user to configure some

channels, for example, for ratiometric operation while others can

be configured for absolute value measurements. The REFSEL bit

in the mode register allows selection of the required reference.

If the REFSEL bit is cleared, the reference selected is REFIN1(+)

–REFIN1(–) for the active channel. If this bit is set, the refer-

ence selected is REFIN2(+) – REFIN2(–) for the active channel.

When the AD7708/AD7718 is configured in 10-channel mode

(CHCON = 1) the user has only one reference option (REFIN1).

The contents of the CHCON bit overrides the REFSEL bit. If

the ADC is configured in five fully-differential or 10 pseudo-

differential input channel mode, the REFSEL bit setting is

irrelevant as only one reference input is available.

The common-mode range for these differential inputs is from

AGND to AVDD. The reference inputs are unbuffered and

therefore excessive R-C source impedances will introduce gain

errors. The nominal reference voltage for specified operation,

VREF, (REFIN1(+)–REFIN1(–) or REFIN2(+)–REFIN2(–)),

is 2.5 V, but the AD7708/AD7718 is functional with reference

voltages from 1 V to AVDD. In applications where the excitation

(voltage or current) for the transducer on the analog input also

drives the reference voltage for the part, the effect of the low

frequency noise in the excitation source will be removed as the

application is ratiometric. If the AD7708/AD7718 is used in a

nonratiometric application, a low noise reference should be

used. Recommended reference voltage sources for the AD7708/

AD7718 include the AD780, REF43, and REF192. It should

also be noted that the reference inputs provide a high impedance,

dynamic load. Because the input impedance of each reference

input is dynamic, resistor/capacitor combinations on these inputs

can cause dc gain errors, depending on the output impedance of

the source that is driving the reference inputs. Reference voltage

sources, like those recommended above (e.g., AD780) will typically

have low output impedances and are therefore tolerant of having

decoupling capacitors on the REFIN(+) without introducing gain

errors in the system. Deriving the reference input voltage across

an external resistor will mean that the reference input sees a

significant external source impedance. External decoupling on

the REFIN(+) and REFIN(–) pins would not be recommended

in this type configuration.

RESET Input

The RESET input on the AD7708/AD7718 resets all the logic,

the digital filter and the analog modulator while all on-chip

registers are reset to their default state. RDY is driven high and

the AD7708/AD7718 ignores all communications to any of its

registers while the RESET input is low. When the RESET input

returns high the AD7708/AD7718 operates with its default setup

conditions and it is necessary to set up all registers and carry out

a system calibration if required after a RESET command.

Power-Down Mode

Loading 0, 0, 0 to the MD2, MD1, MD0 bits in the ADC mode

register places the ADC in device power-down mode. Device

power-down mode is the default condition for the AD7708/

AD7718 on power-up. The ADC retains the contents of all its

on-chip registers (including the data register) while in power-

down. The device power-down mode does not affect the digital

interface, but does affect the status of the RDY pin. Writing the

AD7708/AD7718 into power-down will reset the RDY line high.

Placing the part in power-down mode reduces the total current

(AIDD + DIDD) to 31 µA max when the part is operated at 5 V

and the oscillator allowed to run during power-down mode.

With the oscillator shut down the total IDD is typically 9 µA.

REV. 0

–39–

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