5962F8957701VYX View Datasheet(PDF) - Aeroflex UTMC
Part Name
Description
Manufacturer
5962F8957701VYX Datasheet PDF : 61 Pages
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MCLKD2
DMAR
DMAG
DMACK
TSCTL
MEMCSO
tSHL1
DMA GRANT RECOGNIZED ON THIS EDGE
tPW2
ADDRESS
DATA
RWR/RRD2
AEN
BURST
tOOZL1
tPHL4
tPHL1
tPHL2
tPZL1
tPHL3
tHLH2
SYMBOL
tSHL16
tPHL1
tPHL21
tPZL16
tHLH2
tPHL3
tPW21
PARAMETER
DMACK↓ to DMAR High Impedance RAD
DMAG↓ to DMACK↓ 3
NON-RAD
DMAG↓ to TSCTL↓
TSCTL↓ to ADDRESS valid RAD
NON-RAD
RWR/RRD↑ to DMACK↑
TSCTL↓ to RWR/RRD↓
DMAG↓ to DMAG↑
MIN
-5
10
0
2x-2MCLK
-2
0
THMC1-10
MCLK-20
MCLK
MAX
+5
10
45
4xMCLK
40
40
THMC1+10
MCLK+20
6xMCLK
UNITS
ns
ns
ns
ns
nnss
ns
ns
ns
tOOZL1
DMAR↓ to BURST↑
-10
10
ns
tPHL4
tPHL4
Notes:
DMAR↓ to DMAG↓ 5
DMAR↓ to DMAG↓ 4
0
3.5 (1.9)
µs
0
1.9 (0.8)
µs
1. Guaranteed by test.
2. See figures 27 & 28 for detailed DMA read and write timing.
3. DMAG must be asserted at least 45ns prior to the rising edge of MCLKD2 in order to be recognized for the next MCLKD2 cycle.
If DMAG is not asserted at least 45ns prior to the rising edge of MCLKD2, DMAG is not recognized until the following MCL
KD2 cycle.
4. Provided MCLK = 12MHz. Number in parentheses indicates the longestDMAR↓ toDMAG↓allowed during worst-case bus switching conditions
in order to meet MIL-STD-1553B RT Response Time. The number not in parentheses applies to all other circumstances.
5. Provided MCLK = 6MHz. Number in parentheses indicates the longest DMAR↓ DMAG↓ allowed during worst-case bus switching conditions
in order to meet MIL-STD-1553B RT Response Time. The number not in parentheses applies to all other circumstances.
6. Tested only at initial qualification, and after any design or process changes which may affect this characteristic.
MCLK = period of the memory clock cycle.
BURST signal is for multiple-word DMA accesses.
THMC1 is equivalent to the positive phase of MCLK (see figure 27).
Figure 26. BURST DMA Timing
BCRTM-43
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