5962G8957701-XC View Datasheet(PDF) - Aeroflex UTMC

Part Name

Description

Manufacturer

5962G8957701-XC

BCRTM

Aeroflex UTMC 

Register 0, bit 0, and all other registers are in the appropriate

state to enable Monitor operation.

Valid Command Received.

COMSTR goes active

• DMA Command Block Read. After receiving

a valid command, the BCRTM initiates a burst

DMA:

DMA arbitration (BURST)

Control Word read

Command Word Write

Data List Pointer read

Data Received.

• Data Word DMA.

The BCRTM initiates a DMA cycle for each Data

Word to store the data in memory, whether the

command was a transmit or receive command to any

valid monitored RT Address.

DMA arbitration

Data Word write (starting at Data List Pointer

address, incremented for each successive

word)

Status Word Received.

• Status Word DMA.

DMA arbitration

Status Word write.

Exception Handling.

If an interrupting condition occurs during the

message, the following occurs:

For High-Priority Interrupts:

HPINT is asserted (if enabled in Register 7).

For message errors, the BCRTM is put in a

hold state until the interrupt is acknowledged

(by writing a “1” to the appropriate bit in

Register 8).

For Standard Interrupts:

DMA arbitration (BURST)

Interrupt Status Word write

Command Block Pointer write

Tail Pointer read (into Register 6)

STDINTP pulses low

STDINTL asserted (if enabled)

Processing continues

Message Completion

Upon completion of the message, the BCRTM initiates

a DMA cycle to update the status word and fetch the

address of the next Monitor Command block:

DMA arbitration (BURST)

Control/ Status Word write

Tail Pointer write

9.0 EXCEPTION HANDLING AND

INTERRUPT LOGGING

The exception handling scheme the BCRTM uses is based

on an interrupt structure and provides a high degree of

flexibility in:

• defining the events that cause an interrupt,

• selecting between High-Priority and Standard

interrupts, and

• selecting the amount of interrupt history retained.

The interrupt structure consists of internal registers that

enable interrupt generation, control bits in the RT and BC

data structures (see the Remote Terminal Descriptor

Definition section, page 23, and the Bus Controller

Command Block definition, page 31), and an Interrupt Log

List that sequentially stores an interrupt events record in

system memory.

The BCRTM generates the Interrupt Log List (see figure

21) to allow the host CPU to view the Standard Interrupt

occurrences in chronological order. Each Interrupt Log List

entry contains three words. The first, the Interrupt Status

Word, indicates the type of interrupt (entries are only for

interrupts enabled). In the BC mode, the second word is a

Command Block Pointer that refers to the corresponding

Command Block. In the RT mode, the second word is a

Descriptor Pointer that refers to the corresponding

subaddress descriptor. The CPU-initialized third word, a

Tail Pointer, is read by the BCRTM to determine the next

Interrupt Log List address. The list length can be as long or

as short as required. The configuration of the Tail Pointers

determines the list length.

The host CPU initializes the list by setting the tail pointers.

This gives flexibility in the list capacity and the ability to

link the list around noncontagious blocks of memory. The

host CPU sets the list’s starting address using the Interrupt

Log List Register. The BCRTM then updates this register

with the address of the next list entry.

The internal High-Priority Interrupt Status/Reset Register

indicates the cause of a High-Priority Interrupt. The High-

Priority Interrupt signal is reset by writing a “1” to the set

bits in this register.

BCRTM-36

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