5962F8957701VZA View Datasheet(PDF) - Aeroflex UTMC

Part Name

Description

Manufacturer

5962F8957701VZA

BCRTM

Aeroflex UTMC 

7.1 BC Functional Operation

The Bus Controller off-loads the host computer of many

functions needed to coordinate 1553B bus data transfers.

Special architectural features provide message- by-message

flexibility. In addition, a programmable interrupt scheme,

programmable intermessage timing delays, and internal

registers enhance the BCRTM’s operation.

The host determines the first Command Block by setting the

initial starting address in the current Command Block

Register. Once set, the BCRTM updates the current

Command Block Register with the next Command Block

Address. The BCRTM then executes the sequential

Command Blocks and counts out message delays (where

programmed) until it encounters the last Command Block

listed (indicated by the End of List bit in the control word).

Interrupts are asserted when enabled events occur (see

section 9.0, Exception Handling and Interrupt Logging).

The functions and their programming instructions are

described below. The registers also contain many

programmable functions and function parameters.

15

14

13

12

11

10

9

8

7

0

MESSAGE

ERROR

SKIP

INTERRUPT

AND

CONTINUE

POLLING

ENABLE

AUTO

RETRY

ENABLE

END

OF

LIST

RT-RT

TRANSFER

MONITOR

RT-RT

TRANSFER

‘TIME DELAY’

Figure 13. Command Word

MESSAGE #1

TDELAY1

MESSAGE #2

TDELAY2

MESSAGE #3

Figure 14. BC Timing Delays

BC Command Block Definition

Each Command Block contains (see figure 10):

A. Head Pointer. Host-written, this location can contain the address of the previous Command Block’s Head Pointer.

The BCRTM does not access this location.

B. Control Word. Host-written, the Control Word contains bit-selectable options and a Message Error bit the

BCRTM provides (see figure 13). The bit definitions follow.

Bit

Number

Description

BIT 15

BIT 14

BIT 13

BIT 12

BIT 11

BIT 10

BIT 9

Message Error. The BCRTM sets this bit when it detects an invalid RT response as defined in

MIL-STD 1553B.

Skip. When set, this bit instructs the BCRTM to skip this Command Block and execute the next.

Interrupt and Continue. If set, a Standard Interrupt is asserted when this block is addressed; operation,

however, continues. Note that this interrupt must also be enabled by setting bit 0 of Register 9.

Polling Enable. Enables the BCRTM’s polling operation.

Auto Retry Enable. When set, the Auto Retry function, governed by the global parameters in the Control

Register, is enabled for this message.

End of List. Set by the CPU, this bit indicates that the BCRTM, upon completion of the current message,

will halt and assert a High-Priority Interrupt. The interrupt must also be

enabled in the High-Priority Interrupt Enable Register.

RT-RT. Set by the CPU, this indicates that this Command Block transacts an RT-RT transfer.

BCRTM-30

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