5962G8957701YC View Datasheet(PDF) - Aeroflex UTMC

Part Name

Description

Manufacturer

5962G8957701YC

BCRTM

Aeroflex UTMC 

5.2 Hardware Interface

The BCRTM provides a simple subsystem interface and

facilitates DMA arbitration. The user can configure the

BCRTM to operate in a variety of memory-processor

environments including pseudo-dual-port RAM and

standard DMA configurations.

For complete circuit description, such as arbitration logic

and I/O, please refer to the appropriate application note.

5.3 CPU Interconnection

Pseudo-Dual-Port RAM Configuration

The BCRTM’s Address and Data buses connect directly to

RAM, with buffers isolating the BCRTM’s buses from those

of the host CPU (figures 3a and 3b). The CPU’s memory

control signals (RD, WR, and MEMCSI) pass through the

BCRTM and connect to memory as RRD, RWR, and

MEMCSO.

Standard DMA Configuration

The BCRTM’s and CPU’s data, address, and control signals

are connected to each other as shown in figures 3c and 3d.

The RWR, RRD, and MEMCSO are activated after DMAG

is asserted.

In either case, the BCRTM’s Address and Data buses remain

in a high-impedance state unless the CS and RD

signals are active, indicating a host register access; or

TSCTL is asserted, indicating a memory access by the

BCRTM. CPU attempts to access BCRTM registers are

ignored during BCRTM memory access. Inhibit DMA

transfers by using the Busy function in the Remote Terminal

Address Register while operating in the Remote

Terminal mode.

The designer can use TSCTL to indicate when the BCRTM

is accessing memory or when the CPU can access memory.

AEN is also available (use is optional), giving the CPU

control over the BCRTM’s Address bus. A DMA Burst

(BURST) signal indicates multiple DMA accesses.

Register Access

Registers 0 through 13 are accessed with the decode of the

four LSBs of the Address bus (A0-A3) and asserting CS.

RAM

16 DATA

16 ADDRESS

BUFFERS

HOST

CPU

CONTROL

BCRTM

(DUAL REDUNDANT)

DUAL

TRANSCEIVER

CONTROL/ARBITRATION

TRANSMITTER

TIMEOUT

XFMR XFMR

BUS A

BUS B

1553 BUS

Figure 3b. CPU/BCRTM Interface -- Pseudo-Dual-Port RAM Configuration

BCRTM-21

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