5962F9670801VXC View Datasheet(PDF) - Intersil
Part Name
Description
Manufacturer
5962F9670801VXC Datasheet PDF : 3 Pages
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ACS280MS
January 1996
Radiation Hardened 9-Bit Odd/
Even Parity Generator Checker
Features
Pinouts
• Devices QML Qualified in Accordance with MIL-PRF-38535
• Detailed Electrical and Screening Requirements are Contained in
SMD# 5962-96708 and Intersil’ QM Plan
• 1.25 Micron Radiation Hardened SOS CMOS
• Total Dose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >300K RAD (Si)
• Single Event Upset (SEU) Immunity: <1 x 10-10 Errors/Bit/Day
(Typ)
• SEU LET Threshold . . . . . . . . . . . . . . . . . . . . . . . >100 MEV-cm2/mg
• Dose Rate Upset . . . . . . . . . . . . . . . . >1011 RAD (Si)/s, 20ns Pulse
• Dose Rate Survivability . . . . . . . . . . . >1012 RAD (Si)/s, 20ns Pulse
• Latch-Up Free Under Any Conditions
• Military Temperature Range . . . . . . . . . . . . . . . . . . -55oC to +125oC
• Significant Power Reduction Compared to ALSTTL Logic
• DC Operating Voltage Range . . . . . . . . . . . . . . . . . . . . 4.5V to 5.5V
• Input Logic Levels
- VIL = 30% of VCC Max
- VIH = 70% of VCC Min
• Input Current ≤ 1µA at VOL, VOH
• Fast Propagation Delay . . . . . . . . . . . . . . . . 23ns (Max), 15ns (Typ)
14 PIN CERAMIC DUAL-IN-LINE
MIL-STD-1835 DESIGNATOR, CDIP2-T14,
LEAD FINISH C
TOP VIEW
I6 1
I7 2
NC 3
I8 4
EVEN 5
ODD 6
GND 7
14 VCC
13 I5
12 I4
11 I3
10 I2
9 I1
8 I0
14 PIN CERAMIC FLATPACK
MIL-STD-1835 DESIGNATOR, CDFP3-F14
LEAD FINISH C
TOP VIEW
Description
I6
1
14
VCC
I7
2
13
I5
The Intersil ACS280MS is a Radiation Hardened 9-bit odd/even parity
generator checker device. Both odd and even parity outputs are available
NC
3
12
I4
for generating or checking parity for words up to 9 bits long. Even parity
I8
4
11
I3
is indicated (EVEN output high) when an even number of data inputs are
EVEN
5
10
I2
high. Odd parity is indicated (ODD output high) when an odd number of
ODD
6
9
I1
data inputs are high. Parity checking for larger words can be accom-
GND
7
8
I0
plished by tying EVEN output to any input of an additional ACS280MS.
The ACS280MS utilizes advanced CMOS/SOS technology to achieve
high-speed operation. This device is a member of a radiation hardened,
high-speed, CMOS/SOS Logic Family.
The ACS280MS is supplied in a 14 lead Ceramic Flatpack (K suffix) or a
Ceramic Dual-In-Line Package (D suffix).
Ordering Information
PART NUMBER
5962F9670801VCC
5962F9670801VXC
ACS280D/Sample
ACS280K/Sample
ACS280HMSR
TEMPERATURE RANGE
-55oC to +125oC
-55oC to +125oC
25oC
25oC
25oC
SCREENING LEVEL
MIL-PRF-38535 Class V
MIL-PRF-38535 Class V
Sample
Sample
Die
PACKAGE
14 Lead SBDIP
14 Lead Ceramic Flatpack
14 Lead SBDIP
14 Lead Ceramic Flatpack
Die
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
1
Spec Number 518819
File Number 3568.1
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